Lines Matching full:loads

175 Loads that partially overlap an earlier store
184 Counts number of loads delayed with at-Retirement block code.
186 loads need to be executed at retirement and wait for all senior stores on
192 Cacheable loads delayed with L1D block code
212 .It Li MEM_INST_RETIRED.LOADS
319 Counts number of loads dispatched from the Reservation Station that bypass
328 Counts the number of loads dispatched from the Reservation Station to the
332 Counts all loads dispatched from the Reservation Station.
376 Counts number of loads that hit the L2 cache.
377 L2 loads include both L1D demand misses as well as L1D prefetches.
378 L2 loads can be rejected for various reasons.
379 Only non rejected loads are counted.
382 Counts the number of loads that miss the L2 cache.
383 L2 loads include both L1D demand misses as well as L1D prefetches.
384 .It Li L2_RQSTS.LOADS
387 L2 loads include both L1D demand misses as well as L1D prefetches.
437 Counts number of L2 data demand loads where the cache line to be loaded is
439 L2 demand loads are both L1D demand misses and L1D prefetches.
442 Counts number of L2 data demand loads where the cache line to be loaded is
444 L2 demand loads are both L1D demand misses and L1D
448 Counts number of L2 data demand loads where the cache line to be loaded is
450 L2 demand loads are both L1D demand misses and
454 Counts number of L2 data demand loads where the cache line to be loaded is
456 L2 demand loads are both L1D demand misses and
461 L2 demand loads are both L1D demand
465 Counts number of L2 prefetch data loads where the cache line to be loaded is
469 Counts number of L2 prefetch data loads where the cache line to be loaded is
475 Counts number of L2 prefetch data loads where the cache line to be loaded is
479 Counts number of L2 prefetch data loads where the cache line to be loaded is
1108 Counts number of retired loads that hit the L1 data cache.
1111 Counts number of retired loads that hit the L2 data cache.
1114 Counts number of retired loads that hit their own, unshared lines in the L3
1118 Counts number of retired loads that hit in a sibling core's L2 (on die
1124 Counts number of retired loads that miss the L3 cache.
1128 Counts number of retired loads that miss the L1D and the address is located
1133 Counts the number of retired loads that missed the DTLB.
1135 This event counts loads from cacheable memory only.
1136 The event does not count loads by software prefetches.
1270 Counts L2 load operations due to HW prefetch or demand loads.