Lines Matching +full:cache +full:- +full:time +full:- +full:ms

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
54 determined at run time by calling
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 253669-043US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
127 M-state initial lookup stat in L3.
129 E-state.
131 S-state.
133 F-state.
137 No details on snoop-related information.
146 A snoop was needed and it hits in at least one snooped cache.
147 Hit denotes a cache-line was valid before snoop effect.
158 A snoop was needed and it HitM-ed in local or remote cache.
159 HitM denotes a cache-line was in modified state before effect as a results of snoop.
165 Target was non-DRAM system address.
173 Configure the PMC to count the number of de-asserted to asserted
200 .Bl -tag -width indent
217 Speculative cache-line split load uops dispatched to
221 Speculative cache-line split Store- address uops
246 Number of cache load STLB hits.
282 Counts 256-bit packed single-precision floating-
286 Counts 256-bit packed double-precision floating-
299 Demand Data Read requests that hit L2 cache.
307 hit the L2 cache.
311 miss the L2 cache.
318 cache.
322 cache.
338 ROs that miss cache lines.
341 RFOs that hit cache lines in E state.
344 RFOs that hit cache lines in M state.
347 RFOs that access cache lines in any state.
350 Not rejected writebacks from L1D to L2 cache lines
354 Not rejected writebacks from L1D to L2 cache lines
358 Not rejected writebacks from L1D to L2 cache lines
362 Not rejected writebacks from L1D to L2 cache lines
366 Not rejected writebacks from L1D to L2 cache.
371 a cache line in the last level cache.
374 This event counts each cache miss condition for
375 references to the last level cache.
382 The core frequency may change from time to time due to power or thermal throttling.
409 Not SW-prefetch load dispatches that hit fill
413 Not SW-prefetch load dispatches that hit fill
417 Hardware Prefetch requests that miss the L1D cache.
418 A request is being counted each time it access the cache
424 L1 data cache.
428 L1D cache lines.
432 from the L1 data cache due to replacement.
435 Cache lines in M state evicted out of L1D due
439 Increments the number of flags-merge uops in
510 when MS busy by DSB.
511 Set Cmask = 1 to count cycles MS is busy.
512 Set Cmask=1 and Edge =1 to count MS activations.
516 when MS is busy by MITE.
521 from MS by either DSB or MITE.
525 Number of Instruction Cache, Streaming Buffer and
526 Victim Cache Misses.
540 Number of cache load STLB hits.
605 Count number of non-delivered uops to RAT per
655 Cycles stalled due to re-order buffer full.
673 Cycles with pending L1 cache miss loads.
713 Counts total number of uops to be dispatched per-
718 Counts total number of uops to be dispatched per-
733 (Event B7H, Umask 01H) Off-core Response Performance
738 (Event BBH, Umask 01H) Off-core Response Performance
743 DTLB flush attempts of the thread-specific entries.
763 Number of assists associated with 256-bit AVX
767 Number of transitions from AVX-256 to legacy SSE
771 Number of transitions from SSE to AVX-256 when
775 Counts the number of micro-ops retired, Use
895 Retired load uops with L1 cache hits as data
899 Retired load uops with L2 cache hits as data
913 the same cache line with data not ready.
917 source in cache serviced the load.
920 Counts the number of times the front end is re-
926 Demand Data Read requests that access L2 cache.
929 RFO requests that access L2 cache.
932 L2 cache accesses when fetching instructions.
935 L2 or LLC HW prefetches that access L2 cache.
938 L1D writebacks that access L2 cache.
941 L2 fill requests that access L2 cache.
944 L2 writebacks that access L2 cache.
950 L2 cache lines in I state filling L2.
953 L2 cache lines in S state filling L2.
956 L2 cache lines in E state filling L2.
957 .It Li L2_LINES-IN.ALL
959 L2 cache lines filling L2.
962 Clean L2 cache lines evicted by demand.
965 Dirty L2 cache lines evicted by demand.
968 Clean L2 cache lines evicted by L2 prefetch.
971 Dirty L2 cache lines evicted by L2 prefetch.
974 Dirty L2 cache lines filling the L2.
1006 .An -nosplit