Lines Matching +full:cache +full:- +full:time +full:- +full:ms

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
57 determined at run time by calling
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
64 .%N "Order Number: 253669-039US"
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
90 .Bl -tag -width indent
92 Configure the Off-core Response bits.
93 .Bl -tag -width indent
130 M-state initial lookup stat in L3.
132 E-state.
134 S-state.
136 F-state.
140 No details on snoop-related information.
149 A snoop was needed and it hits in at least one snooped cache.
150 Hit denotes a cache-line was valid before snoop effect.
161 A snoop was needed and it HitM-ed in local or remote cache.
162 HitM denotes a cache-line was in modified state before effect as a results of snoop.
168 Target was non-DRAM system address.
176 Configure the PMC to count the number of de-asserted to asserted
203 .Bl -tag -width indent
218 Speculative cache-line split load uops dispatched to L1D.
221 Speculative cache-line split Store-address uops dispatched to L1D.
241 Number of cache load STLB hits.
273 Counts 256-bit packed single-precision floating-point instructions.
276 Counts 256-bit packed double-precision floating-point instructions.
286 Demand Data Read requests that hit L2 cache.
292 Counts the number of store RFO requests that hit the L2 cache.
295 Counts the number of store RFO requests that miss the L2 cache.
301 Number of instruction fetches that hit the L2 cache.
304 Number of instruction fetches that missed the L2 cache.
319 RFOs that miss cache lines.
322 RFOs that hit cache lines in E state.
325 RFOs that hit cache lines in M state.
328 RFOs that access cache lines in any state.
331 Not rejected writebacks from L1D to L2 cache lines in E state.
334 Not rejected writebacks from L1D to L2 cache lines in M state.
337 This event counts requests originating from the core that reference a cache
338 line in the last level cache.
341 This event counts each cache miss condition for references to the last level
342 cache.
347 The core frequency may change from time to time due to power or thermal
373 Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
376 Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
379 Hardware Prefetch requests that miss the L1D cache.
380 A request is being counted each time it access the cache & miss it, including
382 This accounts for both L1 streamer and IP-based (IPP) HW prefetchers.
385 Counts the number of lines brought into the L1 data cache.
388 Counts the number of allocations of modified L1D cache lines.
391 Counts the number of modified lines evicted from the L1 data cache due to
395 Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line
399 Increments the number of flags-merge uops in flight each cycle.
463 Increment each cycle # of uops delivered to IDQ when MS busy by DSB.
464 Set Cmask = 1 to count cycles MS is busy.
465 Set Cmask=1 and Edge=1 to count MS activations.
469 Increment each cycle # of uops delivered to IDQ when MS is busy by MITE.
474 Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE.
479 Number of Instruction Cache, Streaming Buffer and Victim Cache Misses.
492 Number of cache load STLB hits.
556 Count number of non-delivered uops to RAT per thread.
603 Cycles stalled due to re-order buffer full.
644 Counts total number of uops to be dispatched per-thread each cycle.
648 Counts total number of uops to be dispatched per-core each cycle.
661 Off-core Response Performance Monitoring; PMC0 only.
665 Off-core Response Performance Monitoring.
670 DTLB flush attempts of the thread-specific entries.
694 Number of assists associated with 256-bit AVX store operations.
700 Number of transitions from SSE to AVX-256 when penalty applicable.
703 Counts the number of micro-ops retired.
813 Retired load uops with L1 cache hits as data sources.
817 Retired load uops with L2 cache hits as data sources.
825 to preceding miss to the same cache line with data not ready.
828 Retired load uops which data sources were LLC hit and cross-core snoop missed in
829 on-pkg core cache.
832 Retired load uops which data sources were LLC and cross-core snoop hits in
833 on-pkg core cache.
842 Retired load uops with unknown information as data source in cache serviced the load.
845 Demand Data Read requests that access L2 cache.
848 RFO requests that access L2 cache.
851 L2 cache accesses when fetching instructions.
854 L2 or LLC HW prefetches that access L2 cache.
857 L1D writebacks that access L2 cache.
860 L2 fill requests that access L2 cache.
863 L2 writebacks that access L2 cache.
869 L2 cache lines in I state filling L2.
873 L2 cache lines in S state filling L2.
877 L2 cache lines in E state filling L2.
879 .It Li L2_LINES-IN.ALL
881 L2 cache lines filling L2.
885 Clean L2 cache lines evicted by demand.
888 Dirty L2 cache lines evicted by demand.
891 Clean L2 cache lines evicted by L2 prefetch.
894 Dirty L2 cache lines evicted by L2 prefetch.
897 Dirty L2 cache lines filling the L2.
929 .An -nosplit