Lines Matching full:loads

112 L2 prefetcher to L3 for loads.
204 Loads blocked by overlapping with store buffer that
206 .It Li MISALIGN_MEM_REF.LOADS
633 Cycles with pending L2 miss loads.
637 Cycles with pending memory loads.
641 Number of loads missed L2.
644 Cycles with pending L1 cache miss loads.
676 Number of DTLB page walker loads that hit in the
680 Number of ITLB page walker loads that hit in the
684 Number of DTLB page walker loads that hit in the L2.
687 Number of ITLB page walker loads that hit in the L2.
690 Number of DTLB page walker loads that hit in the L3.
693 Number of ITLB page walker loads that hit in the L3.
696 Number of DTLB page walker loads from memory.
699 Number of ITLB page walker loads from memory.
803 Randomly sampled loads whose latency is above a user defined threshold.
804 A small fraction of the overall loads are sampled due to randomization.