Lines Matching +full:cache +full:- +full:time +full:- +full:ms

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
54 determined at run time by calling
59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%N "Order Number 325462-050US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
95 Configure the PMC to count the number of de-asserted to asserted
121 Events that require core-specificity to be specified use a
127 .Bl -tag -width indent
143 .Bl -tag -width indent
159 .Bl -tag -width "exclude"
171 Events that require a cache coherence qualifier to be specified use an
177 .Bl -tag -width indent
179 Count cache lines in the exclusive state.
181 Count cache lines in the invalid state.
183 Count cache lines in the modified state.
185 Count cache lines in the shared state.
199 .Bl -tag -width indent
215 .Bl -tag -width indent
225 .Bl -tag -width indent
235 at the right time.
239 cache line boundary splits.
243 cache line boundary splits.
263 Data cache.
267 The number of load micro-ops retired that hit L2.
270 The number of load micro-ops retired that missed L2.
289 Every cycle when a D-side (walks due to a load) page walk is in progress.
291 page-walks.
296 Every cycle when a I-side (walks due to an instruction fetch) page walk is in
299 page-walks.
308 the total number of L2 cache references and the number of L2 cache misses
314 references a cache line in the L2 cache.
321 The XQ may reject transactions from the L2Q (non-cacheable
322 requests), BBS (L2 misses) and WOB (L2 write-back victims)
340 In mobile systems the core frequency may change from time to time.
341 For this reason this event may have a changing ratio with regards to time.
346 In mobile systems the core frequency may change from time.
348 is running at the maximum frequency all the time.
351 The number of instruction fetches from the instruction cache.
354 The number of instruction fetches that miss the Instruction cache or produce
376 For instructions that consist of multiple micro-ops, this event counts the
377 retirement of the last micro-op of the instruction.
380 .It Li UOPS_RETIRED.MS
382 The number of micro-ops retired that were supplied from MSROM.
385 The number of micro-ops retired.
389 Self-modifying code causes a severe penalty in all Intel
475 The number of cycles when the front-end does not provide any
479 The number of cycles when the front-end does not provide any
523 .An -nosplit