Lines Matching +full:a +full:- +full:f0 +full:- +full:9
2 # Copyright 2012-2016 The OpenSSL Project Authors. All Rights Reserved.
5 # this file except in compliance with the License. You can obtain a copy
18 # store" which cancels "read" in "read-update-write" on cache lines.
21 # usual benchmarks, on the contrary you can notice that single-thread
31 for (@_) { $::abibits=64 if (/\-m64/ || /\-xarch\=v9/); }
48 save %sp, -$::frame, %sp
58 ldd [$ivec + 0], %f0 ! load ivec
62 faligndata %f0, %f2, %f0
67 ld [$ivec + 0], %f0
111 fxor %f12, %f0, %f0 ! ^= ivec
121 std %f0, [$out + 0]
127 st %f0, [$ivec + 0]
136 std %f0, [$ivec + 0] ! write out ivec
145 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
148 faligndata %f0, %f0, %f4 ! handle unaligned output
149 faligndata %f0, %f2, %f6
162 st %f0, [$ivec + 0]
171 std %f0, [$ivec + 0] ! write out ivec
180 faligndata %f0, %f0, %f4
181 faligndata %f0, %f2, %f6
221 fxor %f12, %f0, %f0 ! ^= ivec
228 stda %f0, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
230 stda %f2, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
239 st %f0, [$ivec + 0]
248 std %f0, [$ivec + 0] ! write out ivec
255 .size ${alg}${bits}_t4_cbc_encrypt,.-${alg}${bits}_t4_cbc_encrypt
266 save %sp, -$::frame, %sp
279 ldd [$ivec + 16], %f0
281 faligndata %f14, %f0, %f14
327 movxtod %o2, %f0
335 fxor %f12, %f0, %f0 ! ^= ivec
343 std %f0, [$out + 0]
367 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
370 faligndata %f0, %f0, %f4 ! handle unaligned output
371 faligndata %f0, %f2, %f6
425 movxtod %o4, %f0
439 fxor %f12, %f0, %f0 ! ^= ivec
449 std %f0, [$out + 0]
474 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
477 faligndata %f0, %f0, %f8 ! handle unaligned output
478 faligndata %f0, %f2, %f0
483 std %f0, [$out + 8]
513 faligndata %f12, %f12, %f0
516 stda %f0, [$ivec + $omask]0xc0
561 movxtod %o4, %f0
575 fxor %f12, %f0, %f0 ! ^= ivec
582 stda %f0, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
584 stda %f2, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
586 stda %f4, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
588 stda %f6, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
617 .size ${alg}${bits}_t4_cbc_decrypt,.-${alg}${bits}_t4_cbc_decrypt
628 save %sp, -$::frame, %sp
692 camellia_f %f18, %f14, %f2, %f0
700 fxor %f10, %f0, %f0 ! ^= inp
706 std %f0, [$out + 0]
715 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
718 faligndata %f0, %f0, %f4 ! handle unaligned output
719 faligndata %f0, %f2, %f6
776 camellia_f %f18, %f14, %f2, %f0
786 fxor %f8, %f0, %f0 ! ^= inp
795 std %f0, [$out + 0]
806 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
809 faligndata %f0, %f0, %f8 ! handle unaligned output
810 faligndata %f0, %f2, %f0
816 std %f0, [$out + 8]
881 camellia_f %f18, %f14, %f2, %f0
892 fxor %f8, %f0, %f0 ! ^= inp
898 stda %f0, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
900 stda %f2, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
902 stda %f4, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
904 stda %f6, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
919 .size ${alg}${bits}_t4_ctr32_encrypt,.-${alg}${bits}_t4_ctr32_encrypt
932 save %sp, -$::frame-16, %sp
936 add %fp, $::bias-16, %o1
940 add %fp, $::bias-16, %l7
942 add %fp, $::bias-8, %l7
953 and $len, -16, $len
1005 movxtod %o0, %f0
1008 fxor %f12, %f0, %f0 ! ^= tweak[0]
1016 fxor %f12, %f0, %f0 ! ^= tweak[0]
1028 std %f0, [$out + 0]
1040 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
1043 faligndata %f0, %f0, %f4 ! handle unaligned output
1044 faligndata %f0, %f2, %f6
1104 movxtod %o0, %f0
1109 fxor %f12, %f0, %f0 ! ^= tweak[0]
1131 fxor %f12, %f0, %f0 ! ^= tweak[0]
1139 std %f0, [$out + 0]
1146 fsrc2 %f4, %f0
1155 2: ldxa [$inp]0x82, %o0 ! avoid read-after-write hazard
1158 faligndata %f0, %f0, %f8 ! handle unaligned output
1159 faligndata %f0, %f2, %f10
1162 faligndata %f6, %f6, %f0
1170 stda %f0, [$out + $omask]0xc0 ! partial store
1175 fsrc2 %f4, %f0
1236 movxtod %o0, %f0
1241 fxor %f12, %f0, %f0 ! ^= tweak[0]
1262 fxor %f12, %f0, %f0 ! ^= tweak[0]
1268 stda %f0, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
1270 stda %f2, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
1272 stda %f4, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
1274 stda %f6, [$out]0xe2 ! ASI_BLK_INIT, T4-specific
1286 fsrc2 %f4, %f0
1298 std %f0, [%fp + $::bias-16] ! copy of output
1299 std %f2, [%fp + $::bias-8]
1302 add %fp, $::bias-16, %l7
1303 add $inp, $ileft, $inp ! original $inp+$len&-15
1304 add $out, $ooff, $out ! original $out+$len&-15
1352 movxtod %o0, %f0
1355 fxor %f12, %f0, %f0 ! ^= tweak[0]
1361 fxor %f12, %f0, %f0 ! ^= tweak[0]
1364 std %f0, [%fp + $::bias-16]
1365 std %f2, [%fp + $::bias-8]
1368 add %fp, $::bias-16, %l7
1369 add $inp, $ileft, $inp ! original $inp+$len&-15
1370 add $out, $ooff, $out ! original $out+$len&-15
1395 .size ${alg}${bits}_t4_xts_${dir}crypt,.-${alg}${bits}_t4_xts_${dir}crypt
1401 # extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
1403 # programmer detect if current CPU is VIS capable at run-time.
1417 return $ref if (!/%f([0-9]{1,2})/);
1421 # re-encode for upper double register addressing
1449 return $ref if (!/%([goli])([0-9])/);
1461 sub unaes_round { # 4-argument instructions
1477 $rs3 = ($rs3 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs3;
1479 return $ref if (!/%f([0-9]{1,2})/);
1483 # re-encode for upper double register addressing
1489 2<<30|$rd<<25|0x19<<19|$rs1<<14|$rs3<<9|$opf<<5|$rs2,
1496 sub unaes_kexpand { # 3-argument instructions
1506 return $ref if (!/%f([0-9]{1,2})/);
1510 # re-encode for upper double register addressing
1523 sub uncamellia_f { # 4-argument instructions
1530 $rs3 = ($rs3 =~ /%f([0-6]*[02468])/) ? (($1|$1>>5)&31) : $rs3;
1532 return $ref if (!/%f([0-9]{1,2})/);
1536 # re-encode for upper double register addressing
1542 2<<30|$rd<<25|0x19<<19|$rs1<<14|$rs3<<9|0xc<<5|$rs2,
1549 sub uncamellia3 { # 3-argument instructions
1559 return $ref if (!/%f([0-9]{1,2})/);
1563 # re-encode for upper double register addressing
1576 sub unmovxtox { # 2-argument instructions
1590 return $ref if (!/%([fgoli])([0-9]{1,2})/);
1594 # re-encode for upper double register addressing
1618 if (defined($opf=$desopf{$mnemonic})) { # 4-arg
1621 return $ref if (!/%f([0-9]{1,2})/);
1625 # re-encode for upper double register addressing
1630 2<<30|0b011001<<19|$opf<<5|$args[0]<<14|$args[1]|$args[2]<<9|$args[3]<<25,
1632 } elsif ($mnemonic eq "des_kexpand") { # 3-arg
1634 return $ref if (!/(%f)?([0-9]{1,2})/);
1638 # re-encode for upper double register addressing
1645 } else { # 2-arg
1647 return $ref if (!/%f([0-9]{1,2})/);
1651 # re-encode for upper double register addressing
1668 s/\b(f[a-z]+2[sd]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})\s*$/$1\t%f0,$2,$3/go;
1670 s/\b(aes_[edk][^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
1673 s/\b(aes_kexpand[02])\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1676 s/\b(camellia_f)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*([%fx0-9]+),\s*(%f[0-9]{1,2})/
1679 s/\b(camellia_[^s]+)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1682 s/\b(des_\w+)\s+(%f[0-9]{1,2}),\s*([%fx0-9]+)(?:,\s*(%f[0-9]{1,2})(?:,\s*(%f[0-9]{1,2}))?)?/
1685 s/\b(mov[ds]to\w+)\s+(%f[0-9]{1,2}),\s*(%[goli][0-7])/
1688 s/\b(mov[xw]to[ds])\s+(%[goli][0-7]),\s*(%f[0-9]{1,2})/
1691 s/\b([fb][^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
1694 …s/\b(umulxhi|bmask|addxc[c]{0,2}|alignaddr[l]*)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7…