Lines Matching defs:OS
87 void Enumeration(raw_ostream &OS, DenseMap<Record *, unsigned> &FeatureMap);
88 void EmitSubtargetInfoMacroCalls(raw_ostream &OS);
89 unsigned FeatureKeyValues(raw_ostream &OS,
91 unsigned CPUKeyValues(raw_ostream &OS,
102 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists);
103 void EmitItineraries(raw_ostream &OS,
106 raw_ostream &OS);
108 raw_ostream &OS);
110 raw_ostream &OS);
111 void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
114 raw_ostream &OS);
116 raw_ostream &OS);
126 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
127 void EmitProcessorModels(raw_ostream &OS);
128 void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
129 void emitSchedModelHelpersImpl(raw_ostream &OS,
131 void emitGenMCSubtargetInfo(raw_ostream &OS);
132 void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS);
134 void EmitSchedModel(raw_ostream &OS);
135 void emitGetMacroFusions(const std::string &ClassName, raw_ostream &OS);
136 void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
137 void ParseFeaturesFunction(raw_ostream &OS);
152 void SubtargetEmitter::Enumeration(raw_ostream &OS,
166 OS << "namespace " << Target << " {\n";
169 OS << "enum {\n";
177 OS << " " << Def->getName() << " = " << i << ",\n";
183 OS << " "
187 OS << "};\n";
188 OS << "} // end namespace " << Target << "\n";
191 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList,
199 OS << "{ { { ";
201 OS << "0x";
202 OS.write_hex(Mask[i]);
203 OS << "ULL, ";
205 OS << "} } }";
210 void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) {
211 OS << "\n#ifdef GET_SUBTARGETINFO_MACRO\n";
234 OS << "GET_SUBTARGETINFO_MACRO(" << FieldName << ", " << Default << ", "
237 OS << "#undef GET_SUBTARGETINFO_MACRO\n";
238 OS << "#endif // GET_SUBTARGETINFO_MACRO\n\n";
240 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
241 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n";
244 OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
252 raw_ostream &OS, const DenseMap<Record *, unsigned> &FeatureMap) {
266 OS << "// Sorted (by key) array of values for CPU features.\n"
283 OS << " { "
289 printFeatureMask(OS, ImpliesList, FeatureMap);
291 OS << " },\n";
300 OS << "};\n";
310 SubtargetEmitter::CPUKeyValues(raw_ostream &OS,
318 OS << "// Sorted (by key) array of values for CPU subtype.\n"
329 OS << " { "
332 printFeatureMask(OS, FeatureList, FeatureMap);
333 OS << ", ";
334 printFeatureMask(OS, TuneFeatureList, FeatureMap);
339 OS << ", &" << ProcModelName << " },\n";
343 OS << "};\n";
439 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
454 OS << "\n// Functional units for \"" << Name << "\"\n"
458 OS << " const InstrStage::FuncUnits " << FUs[j]->getName()
461 OS << "} // end namespace " << Name << "FU\n";
465 OS << "\n// Pipeline forwarding paths for itineraries \"" << Name
469 OS << " const unsigned NoBypass = 0;\n";
471 OS << " const unsigned " << BPs[j]->getName() << " = 1 << " << j
474 OS << "} // end namespace " << Name << "Bypass\n";
603 OS << StageTable;
604 OS << OperandCycleTable;
605 OS << BypassTable;
615 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
639 OS << "\n";
640 OS << "static const llvm::InstrItinerary ";
643 OS << ItinsDef->getName() << "[] = {\n";
651 OS << " { " << Intinerary.NumMicroOps << ", " << Intinerary.FirstStage
657 OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
659 OS << "};\n";
666 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
668 OS << " ";
671 OS << V << Separator << " // " << Name;
673 OS << "MCSchedModel::Default" << Name << Separator;
674 OS << '\n';
678 const CodeGenProcModel &ProcModel, raw_ostream &OS) {
679 OS << "\nstatic const unsigned " << ProcModel.ModelName
692 OS << " " << ProcModel.getProcResourceIdx(RU) << ", ";
695 OS << " // " << PRDef->getName() << "\n";
697 OS << "};\n";
701 raw_ostream &OS) {
710 OS << ReorderBufferSize << ", // ReorderBufferSize\n ";
711 OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n ";
716 unsigned NumCostEntries, raw_ostream &OS) {
718 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles);
720 OS << "nullptr,\n 0";
722 OS << ", // Number of register files.\n ";
724 OS << ProcModel.ModelName << "RegisterCosts,\n ";
726 OS << "nullptr,\n ";
727 OS << NumCostEntries << ", // Number of register cost entries.\n";
732 raw_ostream &OS) {
739 OS << "\n// {RegisterClassID, Register Cost, AllowMoveElimination }\n";
740 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
750 OS << " { ";
753 OS << Rec->getValueAsString("Namespace") << "::";
754 OS << Rec->getName() << "RegClassID, " << RC.Cost << ", "
758 OS << "};\n";
761 OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl, "
763 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
770 OS << " { ";
771 OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", ";
773 OS << NumCostEntries << ", " << CostTblIndex << ", "
778 OS << "};\n";
784 raw_ostream &OS) {
791 OS << " " << QueueID << ", // Resource Descriptor for the Load Queue\n";
800 OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n";
804 raw_ostream &OS) {
807 unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS);
810 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
814 EmitRetireControlUnitInfo(ProcModel, OS);
819 NumCostEntries, OS);
822 EmitLoadStoreQueueInfo(ProcModel, OS);
824 OS << "};\n";
828 raw_ostream &OS) {
829 EmitProcessorResourceSubUnits(ProcModel, OS);
831 OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n";
832 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
862 OS << " {\"" << PRDef->getName() << "\", ";
864 OS.indent(15 - PRDef->getName().size());
865 OS << NumUnits << ", " << SuperIdx << ", " << BufferSize << ", ";
867 OS << ProcModel.ModelName << "ProcResourceSubUnits + "
870 OS << "nullptr";
872 OS << "}, // #" << i + 1;
874 OS << ", Super=" << SuperDef->getName();
875 OS << "\n";
877 OS << "};\n";
1357 raw_ostream &OS) {
1359 OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n"
1366 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
1370 OS << ',';
1371 OS << " // #" << WPRIdx << '\n';
1373 OS << "}; // " << Target << "WriteProcResTable\n";
1376 OS << "\n// {Cycles, WriteResourceID}\n"
1383 OS << " {" << format("%2d", WLEntry.Cycles) << ", "
1386 OS << ',';
1387 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
1389 OS << "}; // " << Target << "WriteLatencyTable\n";
1392 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1399 OS << " {" << RAEntry.UseIdx << ", "
1403 OS << ',';
1404 OS << " // #" << RAIdx << '\n';
1406 OS << "}; // " << Target << "ReadAdvanceTable\n";
1418 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO,"
1420 OS << "static const llvm::MCSchedClassDesc " << PI->ModelName
1427 OS << " {DBGFIELD(\"InvalidSchedClass\") "
1434 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
1436 OS.indent(18 - SchedClass.Name.size());
1437 OS << MCDesc.NumMicroOps << ", " << (MCDesc.BeginGroup ? "true" : "false")
1447 OS << "}; // " << PI->ModelName << "SchedClasses\n";
1451 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
1456 EmitExtraProcessorInfo(PM, OS);
1459 EmitProcessorResources(PM, OS);
1466 OS << "\n";
1467 OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n";
1468 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ',');
1469 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ',');
1470 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ',');
1471 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ',');
1472 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ',');
1473 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ',');
1478 OS << " " << (PostRAScheduler ? "true" : "false") << ", // "
1484 OS << " " << (CompleteModel ? "true" : "false") << ", // "
1490 OS << " " << (EnableIntervals ? "true" : "false") << ", // "
1493 OS << " " << PM.Index << ", // Processor ID\n";
1495 OS << " " << PM.ModelName << "ProcResources"
1504 OS << " nullptr, nullptr, 0, 0,"
1507 OS << " " << PM.ItinsDef->getName() << ",\n";
1509 OS << " nullptr, // No Itinerary\n";
1511 OS << " &" << PM.ModelName << "ExtraInfo,\n";
1513 OS << " nullptr // No extra processor descriptor\n";
1514 OS << "};\n";
1521 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
1522 OS << "#ifdef DBGFIELD\n"
1534 EmitStageAndOperandCycleData(OS, ProcItinLists);
1535 EmitItineraries(OS, ProcItinLists);
1537 OS << "\n// ===============================================================\n"
1544 EmitSchedClassTables(SchedTables, OS);
1546 OS << "\n#undef DBGFIELD\n";
1549 EmitProcessorModels(OS);
1552 static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
1564 OS << Buffer;
1574 raw_ostream &OS) {
1622 OS << Buffer;
1627 static void emitSchedModelHelperEpilogue(raw_ostream &OS,
1630 OS << " // Don't know how to resolve this scheduling class.\n"
1635 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n";
1681 raw_ostream &OS, bool OnlyExpandMCInstPredicates) {
1687 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates);
1698 OS << " switch (SchedClass) {\n";
1704 OS << " case " << VC << ": // " << SC.Name << '\n';
1710 OS << " ";
1714 OS << (OnlyExpandMCInstPredicates
1717 OS << PI << ") ";
1718 OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName << '\n';
1743 emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);
1747 PE, OS);
1749 OS << " }\n";
1756 OS << " return " << SC.Index << ";\n";
1757 OS << " break;\n";
1760 OS << " };\n";
1762 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates);
1766 raw_ostream &OS) {
1767 OS << "unsigned " << ClassName
1772 emitPredicateProlog(Records, OS);
1775 emitSchedModelHelpersImpl(OS);
1777 OS << "} // " << ClassName << "::resolveSchedClass\n\n";
1779 OS << "unsigned " << ClassName
1793 PE.expandSTIPredicate(OS, Fn);
1797 raw_ostream &OS) {
1824 OS << "unsigned " << ClassName << "::getHwModeSet() const {\n";
1825 OS << " // Collect HwModes and store them as a bit set.\n";
1826 OS << " unsigned Modes = 0;\n";
1829 OS << " if (checkFeatures(\"" << HM.Features << "\")) Modes |= (1 << "
1832 OS << " return Modes;\n}\n";
1836 OS << " case HwMode_" << ModeType << ":\n"
1846 OS << "unsigned " << ClassName
1848 OS << " unsigned Modes = getHwModeSet();\n\n";
1849 OS << " if (!Modes)\n return Modes;\n\n";
1850 OS << " switch (type) {\n";
1851 OS << " case HwMode_Default:\n return llvm::countr_zero(Modes) + 1;\n";
1855 OS << " }\n";
1856 OS << " llvm_unreachable(\"unexpected HwModeType\");\n"
1862 raw_ostream &OS) {
1866 OS << "std::vector<MacroFusionPredTy> " << ClassName
1868 OS.indent(2) << "std::vector<MacroFusionPredTy> Fusions;\n";
1871 OS.indent(2) << "if (hasFeature(" << Target << "::" << Name
1875 OS.indent(2) << "return Fusions;\n";
1876 OS << "}\n";
1881 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) {
1886 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1889 OS << Target;
1890 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, "
1897 OS << "}\n";
1902 OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
1905 OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
1915 OS << " if (Bits[" << Target << "::" << Instance << "]) " << FieldName
1918 OS << " if (Bits[" << Target << "::" << Instance << "] && " << FieldName
1922 OS << "}\n";
1925 void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
1926 OS << "namespace " << Target << "_MC {\n"
1929 emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true);
1930 OS << "}\n";
1931 OS << "} // end namespace " << Target << "_MC\n\n";
1933 OS << "struct " << Target
1935 OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT,\n"
1950 OS << " }\n";
1952 OS << " unsigned getHwModeSet() const override;\n";
1953 OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
1957 OS << " bool isCPUStringValid(StringRef CPU) const override {\n"
1961 OS << "};\n";
1962 EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS);
1965 void SubtargetEmitter::EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS) {
1966 OS << "\n#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n";
1967 OS << "#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n";
1973 PE.expandSTIPredicate(OS, Fn);
1975 OS << "#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n";
1977 OS << "\n#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n";
1978 OS << "#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n\n";
1985 PE.expandSTIPredicate(OS, Fn);
1987 OS << "#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n\n";
1993 void SubtargetEmitter::run(raw_ostream &OS) {
1994 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
1996 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
1997 OS << "#undef GET_SUBTARGETINFO_ENUM\n\n";
2001 OS << "namespace llvm {\n";
2002 Enumeration(OS, FeatureMap);
2003 OS << "} // end namespace llvm\n\n";
2004 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
2006 EmitSubtargetInfoMacroCalls(OS);
2008 OS << "namespace llvm {\n";
2010 OS << "namespace {\n";
2012 unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap);
2013 OS << "\n";
2014 EmitSchedModel(OS);
2015 OS << "\n";
2016 unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
2017 OS << "\n";
2019 OS << "} // end anonymous namespace\n\n";
2023 emitGenMCSubtargetInfo(OS);
2025 OS << "\nstatic inline MCSubtargetInfo *create" << Target
2029 OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
2031 OS << " return new " << Target
2034 OS << Target << "FeatureKV, ";
2036 OS << "std::nullopt, ";
2038 OS << Target << "SubTypeKV, ";
2040 OS << "std::nullopt, ";
2041 OS << '\n';
2042 OS.indent(22);
2043 OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "
2045 OS << '\n';
2046 OS.indent(22);
2048 OS << Target << "Stages, " << Target << "OperandCycles, " << Target
2051 OS << "nullptr, nullptr, nullptr";
2052 OS << ");\n}\n\n";
2054 OS << "} // end namespace llvm\n\n";
2056 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
2058 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
2059 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n";
2061 OS << "#include \"llvm/Support/Debug.h\"\n";
2062 OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
2064 OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
2065 ParseFeaturesFunction(OS);
2067 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
2070 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
2071 OS << "#undef GET_SUBTARGETINFO_HEADER\n\n";
2074 OS << "namespace llvm {\n";
2075 OS << "class DFAPacketizer;\n";
2076 OS << "namespace " << Target << "_MC {\n"
2080 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
2093 OS << " unsigned getHwModeSet() const override;\n";
2094 OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
2098 OS << " std::vector<MacroFusionPredTy> getMacroFusions() const "
2104 PE.expandSTIPredicate(OS, Fn);
2106 OS << "};\n"
2109 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
2111 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
2112 OS << "#undef GET_SUBTARGETINFO_CTOR\n\n";
2114 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n";
2115 OS << "namespace llvm {\n";
2116 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
2117 OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n";
2118 OS << "extern const llvm::MCWriteProcResEntry " << Target
2120 OS << "extern const llvm::MCWriteLatencyEntry " << Target
2122 OS << "extern const llvm::MCReadAdvanceEntry " << Target
2126 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
2127 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
2128 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
2131 OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
2135 OS << " : TargetSubtargetInfo(TT, AArch64::resolveCPUAlias(CPU),\n"
2138 OS << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
2140 OS << "ArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
2142 OS << "std::nullopt, ";
2144 OS << "ArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
2146 OS << "std::nullopt, ";
2147 OS << '\n';
2148 OS.indent(24);
2149 OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "
2151 OS << '\n';
2152 OS.indent(24);
2154 OS << Target << "Stages, " << Target << "OperandCycles, " << Target
2157 OS << "nullptr, nullptr, nullptr";
2158 OS << ") {}\n\n";
2160 EmitSchedModelHelpers(ClassName, OS);
2161 EmitHwModeCheck(ClassName, OS);
2162 emitGetMacroFusions(ClassName, OS);
2164 OS << "} // end namespace llvm\n\n";
2166 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
2168 EmitMCInstrAnalysisPredicateFunctions(OS);