Lines Matching +full:isa +full:- +full:extensions
1 //===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // and RISCVISAInfo.cpp to parse the RISC-V CPUs and extensions.
12 //===----------------------------------------------------------------------===//
22 StringRef Name = R->getValueAsString("Name");
23 Name.consume_front("experimental-");
28 const std::vector<Record *> &Extensions,
33 OS << "Extensions[] = {\n";
35 for (Record *R : Extensions) {
36 if (R->getValueAsBit("Experimental") != Experimental)
40 << R->getValueAsInt("MajorVersion") << ", "
41 << R->getValueAsInt("MinorVersion") << "}},\n";
51 std::vector<Record *> Extensions =
53 llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) {
57 if (!Extensions.empty()) {
58 printExtensionTable(OS, Extensions, /*Experimental=*/false);
59 printExtensionTable(OS, Extensions, /*Experimental=*/true);
67 if (!Extensions.empty()) {
69 for (Record *Ext : Extensions) {
70 auto ImpliesList = Ext->getValueAsListOfDefs("Implies");
77 if (!ImpliedExt->isSubClassOf("RISCVExtension"))
92 // in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
98 RISCVISAUtils::OrderedExtensionMap Extensions;
104 if (Feature->isSubClassOf("RISCVExtension")) {
105 unsigned Major = Feature->getValueAsInt("MajorVersion");
106 unsigned Minor = Feature->getValueAsInt("MinorVersion");
107 Extensions[FeatureName.str()] = {Major, Minor};
122 for (auto const &Ext : Extensions)
135 if (Rec->getValueAsBit("Experimental") != Experimental)
138 StringRef Name = Rec->getValueAsString("Name");
139 Name.consume_front("experimental-");
141 printMArch(OS, Rec->getValueAsListOfDefs("Implies"));
157 return Rec->getValueAsBit("Experimental");
176 Rec->getValueAsListOfDefs("Features");
178 return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
182 return Feature->getValueAsString("Name") == "unaligned-vector-mem";
185 OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
188 StringRef MArch = Rec->getValueAsString("DefaultMarch");
206 OS << "TUNE_PROC(" << Rec->getName() << ", "
207 << "\"" << Rec->getValueAsString("Name") << "\")\n";
215 std::vector<Record *> Extensions =
217 llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) {
227 for (const Record *Rec : Extensions) {
228 unsigned GroupIDVal = Rec->getValueAsInt("GroupID");
229 unsigned BitPosVal = Rec->getValueAsInt("BitPos");
231 StringRef ExtName = Rec->getValueAsString("Name");
232 ExtName.consume_front("experimental-");
255 static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
256 "Generate the list of CPUs and extensions for "
257 "RISC-V");