Lines Matching defs:OrigReg

4485   const SCEV *OrigReg;
4488       : LUIdx(LI), Imm(I), OrigReg(R) {}
4498   OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx
4548       const SCEV *OrigReg = J->second;
4551       const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg);
4553       if (!isa<SCEVConstant>(OrigReg) &&
4555         LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg
4565         LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg
4593             WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg));
4608     const SCEV *OrigReg = WI.OrigReg;
4610     Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType());
4623       if (F.ScaledReg == OrigReg) {
4661           if (BaseReg != OrigReg)
4672                 mayUsePostIncMode(TTI, LU, OrigReg, this->L, SE))