Lines Matching +full:gcc +full:- +full:msm8994
1 //===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
18 #include "llvm/Config/llvm-config.h"
25 // Include the platform-specific parts of this class.
54 #define DEBUG_TYPE "host-detection"
56 //===----------------------------------------------------------------------===//
60 //===----------------------------------------------------------------------===//
78 // and so we must use an operating-system interface to determine the current
117 CPULen = CIP - CPUStart;
184 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
185 if (Hardware.ends_with("MSM8994") || Hardware.ends_with("MSM8996"))
186 return "cortex-a53";
193 // and is used in programs like sys-utils
195 .Case("0x926", "arm926ej-s")
197 .Case("0xb36", "arm1136j-s")
198 .Case("0xb56", "arm1156t2-s")
199 .Case("0xb76", "arm1176jz-s")
200 .Case("0xc05", "cortex-a5")
201 .Case("0xc07", "cortex-a7")
202 .Case("0xc08", "cortex-a8")
203 .Case("0xc09", "cortex-a9")
204 .Case("0xc0f", "cortex-a15")
205 .Case("0xc0e", "cortex-a17")
206 .Case("0xc20", "cortex-m0")
207 .Case("0xc23", "cortex-m3")
208 .Case("0xc24", "cortex-m4")
209 .Case("0xc27", "cortex-m7")
210 .Case("0xd20", "cortex-m23")
211 .Case("0xd21", "cortex-m33")
212 .Case("0xd24", "cortex-m52")
213 .Case("0xd22", "cortex-m55")
214 .Case("0xd23", "cortex-m85")
215 .Case("0xc18", "cortex-r8")
216 .Case("0xd13", "cortex-r52")
217 .Case("0xd16", "cortex-r52plus")
218 .Case("0xd15", "cortex-r82")
219 .Case("0xd14", "cortex-r82ae")
220 .Case("0xd02", "cortex-a34")
221 .Case("0xd04", "cortex-a35")
222 .Case("0xd03", "cortex-a53")
223 .Case("0xd05", "cortex-a55")
224 .Case("0xd46", "cortex-a510")
225 .Case("0xd80", "cortex-a520")
226 .Case("0xd88", "cortex-a520ae")
227 .Case("0xd07", "cortex-a57")
228 .Case("0xd06", "cortex-a65")
229 .Case("0xd43", "cortex-a65ae")
230 .Case("0xd08", "cortex-a72")
231 .Case("0xd09", "cortex-a73")
232 .Case("0xd0a", "cortex-a75")
233 .Case("0xd0b", "cortex-a76")
234 .Case("0xd0e", "cortex-a76ae")
235 .Case("0xd0d", "cortex-a77")
236 .Case("0xd41", "cortex-a78")
237 .Case("0xd42", "cortex-a78ae")
238 .Case("0xd4b", "cortex-a78c")
239 .Case("0xd47", "cortex-a710")
240 .Case("0xd4d", "cortex-a715")
241 .Case("0xd81", "cortex-a720")
242 .Case("0xd89", "cortex-a720ae")
243 .Case("0xd87", "cortex-a725")
244 .Case("0xd44", "cortex-x1")
245 .Case("0xd4c", "cortex-x1c")
246 .Case("0xd48", "cortex-x2")
247 .Case("0xd4e", "cortex-x3")
248 .Case("0xd82", "cortex-x4")
249 .Case("0xd85", "cortex-x925")
250 .Case("0xd4a", "neoverse-e1")
251 .Case("0xd0c", "neoverse-n1")
252 .Case("0xd49", "neoverse-n2")
253 .Case("0xd8e", "neoverse-n3")
254 .Case("0xd40", "neoverse-v1")
255 .Case("0xd4f", "neoverse-v2")
256 .Case("0xd84", "neoverse-v3")
257 .Case("0xd83", "neoverse-v3ae")
301 .Case("0x800", "cortex-a73") // Kryo 2xx Gold
302 .Case("0x801", "cortex-a73") // Kryo 2xx Silver
303 .Case("0x802", "cortex-a75") // Kryo 3xx Gold
304 .Case("0x803", "cortex-a75") // Kryo 3xx Silver
305 .Case("0x804", "cortex-a76") // Kryo 4xx Gold
306 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
309 .Case("0x001", "oryon-1")
334 return "exynos-m3";
336 return "exynos-m4";
343 .Case("0xd49", "neoverse-n2")
365 case 2094: // z9-109 not supported by LLVM
427 Pos += sizeof("machine = ") - 1;
454 .Case("sifive,u74-mc", "sifive-u74")
455 .Case("sifive,bullet0", "sifive-u74")
534 // or test-suite, but are used in external projects e.g. libstdcxx
563 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
569 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
637 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
645 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
696 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
697 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
701 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
703 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
725 CPU = "pentium-mmx";
735 // Pentium Dual-Core processor, Intel Xeon processor, model
808 case 0xa5: // Comet Lake-H/S
809 case 0xa6: // Comet Lake-U
832 CPU = "skylake-avx512";
847 CPU = "icelake-client";
888 CPU = "arrowlake-s";
909 CPU = "graniterapids-d";
917 CPU = "icelake-server";
957 CPU = "goldmont-plus";
998 // They're used above to keep the code in sync with compiler-rt.
1003 CPU = "icelake-client";
1011 CPU = "skylake-avx512";
1040 CPU = "pentium-m";
1089 CPU = "k6-2";
1093 CPU = "k6-3";
1102 CPU = "athlon-xp";
1109 CPU = "k8-sse3";
1139 break; // 60h-7Fh: Excavator
1144 break; // 30h-3Fh: Steamroller
1149 break; // 02h, 10h-1Fh: Piledriver
1153 break; // 00h-0Fh: Bulldozer
1168 // Family 17h Models 30h-3Fh (Starship) Zen 2
1170 // Family 17h Models 60h-67h (Renoir) Zen 2
1171 // Family 17h Models 68h-6Fh (Lucienne) Zen 2
1172 // Family 17h Models 70h-7Fh (Matisse) Zen 2
1173 // Family 17h Models 84h-87h (ProjectX) Zen 2
1174 // Family 17h Models 90h-97h (VanGogh) Zen 2
1175 // Family 17h Models 98h-9Fh (Mero) Zen 2
1176 // Family 17h Models A0h-AFh (Mendocino) Zen 2
1182 // Family 17h Models 10h-1Fh (Raven1) Zen
1183 // Family 17h Models 10h-1Fh (Picasso) Zen+
1184 // Family 17h Models 20h-2Fh (Raven2 x86) Zen
1195 // Family 19h Models 00h-0Fh (Genesis, Chagall) Zen 3
1196 // Family 19h Models 20h-2Fh (Vermeer) Zen 3
1197 // Family 19h Models 30h-3Fh (Badami) Zen 3
1198 // Family 19h Models 40h-4Fh (Rembrandt) Zen 3+
1199 // Family 19h Models 50h-5Fh (Cezanne) Zen 3
1206 // Family 19h Models 10h-1Fh (Stones; Storm Peak) Zen 4
1207 // Family 19h Models 60h-6Fh (Raphael) Zen 4
1208 // Family 19h Models 70h-77h (Phoenix, Hawkpoint1) Zen 4
1209 // Family 19h Models 78h-7Fh (Phoenix 2, Hawkpoint2) Zen 4
1210 // Family 19h Models A0h-AFh (Stones-Dense) Zen 4
1220 // Models 00h-0Fh (Breithorn).
1221 // Models 10h-1Fh (Breithorn-Dense).
1222 // Models 20h-2Fh (Strix 1).
1223 // Models 30h-37h (Strix 2).
1224 // Models 38h-3Fh (Strix 3).
1225 // Models 40h-4Fh (Granite Ridge).
1226 // Models 50h-5Fh (Weisshorn).
1227 // Models 60h-6Fh (Krackan1).
1228 // Models 70h-77h (Sarlak).
1393 // same or similar to compiler-rt.
1460 StringRef Content = P ? P->getBuffer() : "";
1466 StringRef Content = P ? P->getBuffer() : "";
1472 StringRef Content = P ? P->getBuffer() : "";
1479 // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1481 // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1487 // The model number is located in the CVT prefix at offset -6 and stored as
1489 uint16_t Id = *(uint16_t *)&CVT[-6];
1520 return "apple-a7";
1522 return "apple-a8";
1524 return "apple-a9";
1526 return "apple-a10";
1528 return "apple-a11";
1530 return "apple-a12";
1532 return "apple-a13";
1534 return "apple-m1";
1536 return "apple-m2";
1538 return "apple-m3";
1541 return "apple-m3";
1589 case 0xc000: // Loongson 64bit, 4-issue
1591 case 0xd000: // Loongson 64bit, 6-issue
1603 StringRef Content = P ? P->getBuffer() : "";
1609 return "generic-rv64";
1611 return "generic-rv32";
1650 .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */)
1651 .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */)
1652 .StartsWith("SPARC-M8", "niagara4" /* "m8" */)
1660 StringRef Content = P ? P->getBuffer() : "";
1670 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);
1671 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1672 ksp->ks_type == KSTAT_TYPE_NAMED)
1675 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1690 .Case("UltraSPARC-I", "ultrasparc")
1691 .Case("UltraSPARC-II", "ultrasparc")
1692 .Case("UltraSPARC-IIe", "ultrasparc")
1693 .Case("UltraSPARC-IIi", "ultrasparc")
1694 .Case("SPARC64-III", "ultrasparc")
1695 .Case("SPARC64-IV", "ultrasparc")
1696 .Case("UltraSPARC-III", "ultrasparc3")
1697 .Case("UltraSPARC-III+", "ultrasparc3")
1698 .Case("UltraSPARC-IIIi", "ultrasparc3")
1699 .Case("UltraSPARC-IIIi+", "ultrasparc3")
1700 .Case("UltraSPARC-IV", "ultrasparc3")
1701 .Case("UltraSPARC-IV+", "ultrasparc3")
1702 .Case("SPARC64-V", "ultrasparc3")
1703 .Case("SPARC64-VI", "ultrasparc3")
1704 .Case("SPARC64-VII", "ultrasparc3")
1705 .Case("UltraSPARC-T1", "niagara")
1706 .Case("UltraSPARC-T2", "niagara2")
1707 .Case("UltraSPARC-T2", "niagara2")
1708 .Case("UltraSPARC-T2+", "niagara2")
1709 .Case("SPARC-T3", "niagara3")
1710 .Case("SPARC-T4", "niagara4")
1711 .Case("SPARC-T5", "niagara4")
1713 .Case("SPARC-M7", "niagara4" /* "niagara7" */)
1714 .Case("SPARC-S7", "niagara4" /* "niagara7" */)
1715 .Case("SPARC-M8", "niagara4" /* "m8" */)
1875 // detecting features using the "-march=native" flag.
1878 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1880 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1881 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1893 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
1899 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
1903 Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
1931 Features["avx10.1-512"] =
1932 Features["avx10.1-256"] && HasLeaf24 && ((EBX >> 18) & 1);
1944 P->getBuffer().split(Lines, "\n");
1965 .Case("fp", "fp-armv8")
1976 .Case("idiva", "hwdiv-arm")
2098 // TODO: Re-enable zacas when it is marked non-experimental again.
2104 // TODO: set unaligned-scalar-mem if RISCV_HWPROBE_KEY_MISALIGNED_PERF returns