Lines Matching +full:16 +full:- +full:bits

1 //===- XtensaInstrFormats.td - Xtensa Instruction Formats --*- tablegen -*-===//
7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9 //===----------------------------------------------------------------------===//
11 // Base class for Xtensa 16 & 24 bit Formats
32   field bits<24> Inst;
33   field bits<24> SoftFail = 0;
36 // Base class for Xtensa 16 bit Format
40   field bits<16> Inst;
41   field bits<16> SoftFail = 0;
45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
48   bits<4> r;
49   bits<4> s;
50   bits<4> t;
52   let Inst{23-20} = op2;
53   let Inst{19-16} = op1;
54   let Inst{15-12} = r;
55   let Inst{11-8} = s;
56   let Inst{7-4} = t;
57   let Inst{3-0} = op0;
60 class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
63   bits<4> r;
64   bits<4> s;
65   bits<4> t;
66   bits<4> imm4;
68   let Inst{23-20} = imm4;
69   let Inst{19-16} = op1;
70   let Inst{15-12} = r;
71   let Inst{11-8} = s;
72   let Inst{7-4} = t;
73   let Inst{3-0} = op0;
76 class RRI8_Inst<bits<4> op0, dag outs, dag ins,
79   bits<4> r;
80   bits<4> s;
81   bits<4> t;
82   bits<8> imm8;
84   let Inst{23-16} = imm8;
85   let Inst{15-12} = r;
86   let Inst{11-8} = s;
87   let Inst{7-4} = t;
88   let Inst{3-0} = op0;
91 class RI16_Inst<bits<4> op0, dag outs, dag ins,
94   bits<4> t;
95   bits<16> imm16;
97   let Inst{23-8} = imm16;
98   let Inst{7-4} = t;
99   let Inst{3-0} = op0;
102 class RSR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
105   bits<8> sr;
106   bits<4> t;
108   let Inst{23-20} = op2;
109   let Inst{19-16} = op1;
110   let Inst{15-8} = sr;
111   let Inst{7-4} = t;
112   let Inst{3-0} = op0;
115 class CALL_Inst<bits<4> op0, dag outs, dag ins,
118   bits<18> offset;
119   bits<2> n;
121   let Inst{23-6} = offset;
122   let Inst{5-4} = n;
123   let Inst{3-0} = op0;
126 class CALLX_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
129   bits<4> r;
130   bits<4> s;
131   bits<2> m;
132   bits<2> n;
134   let Inst{23-20} = op2;
135   let Inst{19-16} = op1;
136   let Inst{15-12} = r;
137   let Inst{11-8} = s;
138   let Inst{7-6} = m;
139   let Inst{5-4} = n;
140   let Inst{3-0} = op0;
143 class BRI8_Inst<bits<4> op0, dag outs, dag ins,
146   bits<8> imm8;
147   bits<4> r;
148   bits<4> s;
149   bits<2> m;
150   bits<2> n;
152   let Inst{23-16} = imm8;
153   let Inst{15-12} = r;
154   let Inst{11-8} = s;
155   let Inst{7-6} = m;
156   let Inst{5-4} = n;
157   let Inst{3-0} = op0;
160 class BRI12_Inst<bits<4> op0, bits<2> n, bits<2> m, dag outs, dag ins,
163   bits<12> imm12;
164   bits<4> s;
166   let Inst{23-12} = imm12;
167   let Inst{11-8} = s;
168   let Inst{7-6} = m;
169   let Inst{5-4} = n;
170   let Inst{3-0} = op0;
173 class RRRN_Inst<bits<4> op0, dag outs, dag ins,
176   bits<4> r;
177   bits<4> s;
178   bits<4> t;
180   let Inst{15-12} = r;
181   let Inst{11-8} = s;
182   let Inst{7-4} = t;
183   let Inst{3-0} = op0;
186 class RI7_Inst<bits<4> op0, bits<1> i, dag outs, dag ins,
189   bits<7> imm7;
190   bits<4> s;
192   let Inst{15-12} = imm7{3-0};
193   let Inst{11-8} = s;
195   let Inst{6-4} = imm7{6-4};
196   let Inst{3-0} = op0;
199 class RI6_Inst<bits<4> op0, bits<1> i,  bits<1> z, dag outs, dag ins,
202   bits<6> imm6;
203   bits<4> s;
205   let Inst{15-12} = imm6{3-0};
206   let Inst{11-8} = s;
209   let Inst{5-4} = imm6{5-4};
210   let Inst{3-0} = op0;