Lines Matching defs:ISD
270 int ISD = TLI->InstructionOpcodeToISD(Opcode);
271 assert(ISD && "Invalid opcode");
273 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
323 ISD = X86ISD::PMULUDQ;
328 if (ISD == ISD::MUL && Op2Info.isConstant() &&
342 if ((ISD == ISD::SDIV || ISD == ISD::SREM) &&
352 if (ISD == ISD::SREM) {
364 if ((ISD == ISD::UDIV || ISD == ISD::UREM) &&
366 if (ISD == ISD::UDIV)
375 { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
376 { ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
377 { ISD::SRA, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
378 { ISD::SHL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
379 { ISD::SRL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
380 { ISD::SRA, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
381 { ISD::SHL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
382 { ISD::SRL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
383 { ISD::SRA, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
388 CostTableLookup(GFNIUniformConstCostTable, ISD, LT.second))
393 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand.
394 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand.
395 { ISD::SRA, MVT::v16i8, { 1, 8, 4, 5 } }, // psrlw, pand, pxor, psubb.
396 { ISD::SHL, MVT::v32i8, { 1, 8, 2, 3 } }, // psllw + pand.
397 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand.
398 { ISD::SRA, MVT::v32i8, { 1, 9, 4, 5 } }, // psrlw, pand, pxor, psubb.
399 { ISD::SHL, MVT::v64i8, { 1, 8, 2, 3 } }, // psllw + pand.
400 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand.
401 { ISD::SRA, MVT::v64i8, { 1, 9, 4, 6 } }, // psrlw, pand, pxor, psubb.
403 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // psllw
404 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw
405 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw
406 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // psllw
407 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw
408 { ISD::SRA, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw
413 CostTableLookup(AVX512BWUniformConstCostTable, ISD, LT.second))
418 { ISD::SHL, MVT::v64i8, { 2, 12, 5, 6 } }, // psllw + pand.
419 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand.
420 { ISD::SRA, MVT::v64i8, { 3, 10, 12, 12 } }, // psrlw, pand, pxor, psubb.
422 { ISD::SHL, MVT::v16i16, { 2, 7, 4, 4 } }, // psllw + split.
423 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split.
424 { ISD::SRA, MVT::v16i16, { 2, 7, 4, 4 } }, // psraw + split.
426 { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } }, // pslld
427 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, // psrld
428 { ISD::SRA, MVT::v8i32, { 1, 1, 1, 1 } }, // psrad
429 { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } }, // pslld
430 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, // psrld
431 { ISD::SRA, MVT::v16i32, { 1, 1, 1, 1 } }, // psrad
433 { ISD::SRA, MVT::v2i64, { 1, 1, 1, 1 } }, // psraq
434 { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } }, // psllq
435 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } }, // psrlq
436 { ISD::SRA, MVT::v4i64, { 1, 1, 1, 1 } }, // psraq
437 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } }, // psllq
438 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, // psrlq
439 { ISD::SRA, MVT::v8i64, { 1, 1, 1, 1 } }, // psraq
441 { ISD::SDIV, MVT::v16i32, { 6 } }, // pmuludq sequence
442 { ISD::SREM, MVT::v16i32, { 8 } }, // pmuludq+mul+sub sequence
443 { ISD::UDIV, MVT::v16i32, { 5 } }, // pmuludq sequence
444 { ISD::UREM, MVT::v16i32, { 7 } }, // pmuludq+mul+sub sequence
449 CostTableLookup(AVX512UniformConstCostTable, ISD, LT.second))
454 { ISD::SHL, MVT::v16i8, { 1, 8, 2, 3 } }, // psllw + pand.
455 { ISD::SRL, MVT::v16i8, { 1, 8, 2, 3 } }, // psrlw + pand.
456 { ISD::SRA, MVT::v16i8, { 2, 10, 5, 6 } }, // psrlw, pand, pxor, psubb.
457 { ISD::SHL, MVT::v32i8, { 2, 8, 2, 4 } }, // psllw + pand.
458 { ISD::SRL, MVT::v32i8, { 2, 8, 2, 4 } }, // psrlw + pand.
459 { ISD::SRA, MVT::v32i8, { 3, 10, 5, 9 } }, // psrlw, pand, pxor, psubb.
461 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw
462 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw
463 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw
464 { ISD::SHL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psllw
465 { ISD::SRL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psrlw
466 { ISD::SRA, MVT::v16i16,{ 2, 2, 1, 2 } }, // psraw
468 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld
469 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld
470 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad
471 { ISD::SHL, MVT::v8i32, { 2, 2, 1, 2 } }, // pslld
472 { ISD::SRL, MVT::v8i32, { 2, 2, 1, 2 } }, // psrld
473 { ISD::SRA, MVT::v8i32, { 2, 2, 1, 2 } }, // psrad
475 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq
476 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq
477 { ISD::SRA, MVT::v2i64, { 2, 3, 3, 3 } }, // psrad + shuffle.
478 { ISD::SHL, MVT::v4i64, { 2, 2, 1, 2 } }, // psllq
479 { ISD::SRL, MVT::v4i64, { 2, 2, 1, 2 } }, // psrlq
480 { ISD::SRA, MVT::v4i64, { 4, 4, 3, 6 } }, // psrad + shuffle + split.
482 { ISD::SDIV, MVT::v8i32, { 6 } }, // pmuludq sequence
483 { ISD::SREM, MVT::v8i32, { 8 } }, // pmuludq+mul+sub sequence
484 { ISD::UDIV, MVT::v8i32, { 5 } }, // pmuludq sequence
485 { ISD::UREM, MVT::v8i32, { 7 } }, // pmuludq+mul+sub sequence
490 CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second))
495 { ISD::SHL, MVT::v16i8, { 2, 7, 2, 3 } }, // psllw + pand.
496 { ISD::SRL, MVT::v16i8, { 2, 7, 2, 3 } }, // psrlw + pand.
497 { ISD::SRA, MVT::v16i8, { 3, 9, 5, 6 } }, // psrlw, pand, pxor, psubb.
498 { ISD::SHL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psllw + pand) + split.
499 { ISD::SRL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psrlw + pand) + split.
500 { ISD::SRA, MVT::v32i8, { 7, 7, 12, 13 } }, // 2*(psrlw, pand, pxor, psubb) + split.
502 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 1 } }, // psllw.
503 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 1 } }, // psrlw.
504 { ISD::SRA, MVT::v8i16, { 1, 2, 1, 1 } }, // psraw.
505 { ISD::SHL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psllw + split.
506 { ISD::SRL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psrlw + split.
507 { ISD::SRA, MVT::v16i16,{ 3, 6, 4, 5 } }, // psraw + split.
509 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 1 } }, // pslld.
510 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 1 } }, // psrld.
511 { ISD::SRA, MVT::v4i32, { 1, 2, 1, 1 } }, // psrad.
512 { ISD::SHL, MVT::v8i32, { 3, 6, 4, 5 } }, // pslld + split.
513 { ISD::SRL, MVT::v8i32, { 3, 6, 4, 5 } }, // psrld + split.
514 { ISD::SRA, MVT::v8i32, { 3, 6, 4, 5 } }, // psrad + split.
516 { ISD::SHL, MVT::v2i64, { 1, 2, 1, 1 } }, // psllq.
517 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 1 } }, // psrlq.
518 { ISD::SRA, MVT::v2i64, { 2, 3, 3, 3 } }, // psrad + shuffle.
519 { ISD::SHL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split.
520 { ISD::SRL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split.
521 { ISD::SRA, MVT::v4i64, { 5, 7, 8, 9 } }, // 2 x psrad + shuffle + split.
523 { ISD::SDIV, MVT::v8i32, { 14 } }, // 2*pmuludq sequence + split.
524 { ISD::SREM, MVT::v8i32, { 18 } }, // 2*pmuludq+mul+sub sequence + split.
525 { ISD::UDIV, MVT::v8i32, { 12 } }, // 2*pmuludq sequence + split.
526 { ISD::UREM, MVT::v8i32, { 16 } }, // 2*pmuludq+mul+sub sequence + split.
533 CostTableLookup(AVXUniformConstCostTable, ISD, LT.second))
538 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand.
539 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand.
540 { ISD::SRA, MVT::v16i8, { 3, 9, 5, 6 } }, // psrlw, pand, pxor, psubb.
542 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw.
543 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw.
544 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw.
546 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld
547 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld.
548 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad.
550 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq.
551 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq.
552 { ISD::SRA, MVT::v2i64, { 3, 5, 6, 6 } }, // 2 x psrad + shuffle.
554 { ISD::SDIV, MVT::v4i32, { 6 } }, // pmuludq sequence
555 { ISD::SREM, MVT::v4i32, { 8 } }, // pmuludq+mul+sub sequence
556 { ISD::UDIV, MVT::v4i32, { 5 } }, // pmuludq sequence
557 { ISD::UREM, MVT::v4i32, { 7 } }, // pmuludq+mul+sub sequence
564 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
569 { ISD::SDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence
570 { ISD::SREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
571 { ISD::UDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence
572 { ISD::UREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
574 { ISD::SDIV, MVT::v32i16, { 6 } }, // vpmulhw sequence
575 { ISD::SREM, MVT::v32i16, { 8 } }, // vpmulhw+mul+sub sequence
576 { ISD::UDIV, MVT::v32i16, { 6 } }, // vpmulhuw sequence
577 { ISD::UREM, MVT::v32i16, { 8 } }, // vpmulhuw+mul+sub sequence
582 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
587 { ISD::SDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence
588 { ISD::SREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
589 { ISD::UDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence
590 { ISD::UREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
592 { ISD::SDIV, MVT::v32i16, { 12 } }, // 2*vpmulhw sequence
593 { ISD::SREM, MVT::v32i16, { 16 } }, // 2*vpmulhw+mul+sub sequence
594 { ISD::UDIV, MVT::v32i16, { 12 } }, // 2*vpmulhuw sequence
595 { ISD::UREM, MVT::v32i16, { 16 } }, // 2*vpmulhuw+mul+sub sequence
597 { ISD::SDIV, MVT::v16i32, { 15 } }, // vpmuldq sequence
598 { ISD::SREM, MVT::v16i32, { 17 } }, // vpmuldq+mul+sub sequence
599 { ISD::UDIV, MVT::v16i32, { 15 } }, // vpmuludq sequence
600 { ISD::UREM, MVT::v16i32, { 17 } }, // vpmuludq+mul+sub sequence
605 CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
610 { ISD::SDIV, MVT::v32i8, { 14 } }, // 2*ext+2*pmulhw sequence
611 { ISD::SREM, MVT::v32i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
612 { ISD::UDIV, MVT::v32i8, { 14 } }, // 2*ext+2*pmulhw sequence
613 { ISD::UREM, MVT::v32i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
615 { ISD::SDIV, MVT::v16i16, { 6 } }, // vpmulhw sequence
616 { ISD::SREM, MVT::v16i16, { 8 } }, // vpmulhw+mul+sub sequence
617 { ISD::UDIV, MVT::v16i16, { 6 } }, // vpmulhuw sequence
618 { ISD::UREM, MVT::v16i16, { 8 } }, // vpmulhuw+mul+sub sequence
620 { ISD::SDIV, MVT::v8i32, { 15 } }, // vpmuldq sequence
621 { ISD::SREM, MVT::v8i32, { 19 } }, // vpmuldq+mul+sub sequence
622 { ISD::UDIV, MVT::v8i32, { 15 } }, // vpmuludq sequence
623 { ISD::UREM, MVT::v8i32, { 19 } }, // vpmuludq+mul+sub sequence
627 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
632 { ISD::SDIV, MVT::v32i8, { 30 } }, // 4*ext+4*pmulhw sequence + split.
633 { ISD::SREM, MVT::v32i8, { 34 } }, // 4*ext+4*pmulhw+mul+sub sequence + split.
634 { ISD::UDIV, MVT::v32i8, { 30 } }, // 4*ext+4*pmulhw sequence + split.
635 { ISD::UREM, MVT::v32i8, { 34 } }, // 4*ext+4*pmulhw+mul+sub sequence + split.
637 { ISD::SDIV, MVT::v16i16, { 14 } }, // 2*pmulhw sequence + split.
638 { ISD::SREM, MVT::v16i16, { 18 } }, // 2*pmulhw+mul+sub sequence + split.
639 { ISD::UDIV, MVT::v16i16, { 14 } }, // 2*pmulhuw sequence + split.
640 { ISD::UREM, MVT::v16i16, { 18 } }, // 2*pmulhuw+mul+sub sequence + split.
642 { ISD::SDIV, MVT::v8i32, { 32 } }, // vpmuludq sequence
643 { ISD::SREM, MVT::v8i32, { 38 } }, // vpmuludq+mul+sub sequence
644 { ISD::UDIV, MVT::v8i32, { 32 } }, // 2*pmuludq sequence + split.
645 { ISD::UREM, MVT::v8i32, { 42 } }, // 2*pmuludq+mul+sub sequence + split.
649 if (const auto *Entry = CostTableLookup(AVXConstCostTable, ISD, LT.second))
654 { ISD::SDIV, MVT::v4i32, { 15 } }, // vpmuludq sequence
655 { ISD::SREM, MVT::v4i32, { 20 } }, // vpmuludq+mul+sub sequence
660 CostTableLookup(SSE41ConstCostTable, ISD, LT.second))
665 { ISD::SDIV, MVT::v16i8, { 14 } }, // 2*ext+2*pmulhw sequence
666 { ISD::SREM, MVT::v16i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
667 { ISD::UDIV, MVT::v16i8, { 14 } }, // 2*ext+2*pmulhw sequence
668 { ISD::UREM, MVT::v16i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
670 { ISD::SDIV, MVT::v8i16, { 6 } }, // pmulhw sequence
671 { ISD::SREM, MVT::v8i16, { 8 } }, // pmulhw+mul+sub sequence
672 { ISD::UDIV, MVT::v8i16, { 6 } }, // pmulhuw sequence
673 { ISD::UREM, MVT::v8i16, { 8 } }, // pmulhuw+mul+sub sequence
675 { ISD::SDIV, MVT::v4i32, { 19 } }, // pmuludq sequence
676 { ISD::SREM, MVT::v4i32, { 24 } }, // pmuludq+mul+sub sequence
677 { ISD::UDIV, MVT::v4i32, { 15 } }, // pmuludq sequence
678 { ISD::UREM, MVT::v4i32, { 20 } }, // pmuludq+mul+sub sequence
682 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second))
687 { ISD::SHL, MVT::v16i8, { 3, 5, 5, 7 } }, // psllw + pand.
688 { ISD::SRL, MVT::v16i8, { 3,10, 5, 8 } }, // psrlw + pand.
689 { ISD::SRA, MVT::v16i8, { 4,12, 8,12 } }, // psrlw, pand, pxor, psubb.
690 { ISD::SHL, MVT::v32i8, { 4, 7, 6, 8 } }, // psllw + pand.
691 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand.
692 { ISD::SRA, MVT::v32i8, { 5,10,10,13 } }, // psrlw, pand, pxor, psubb.
693 { ISD::SHL, MVT::v64i8, { 4, 7, 6, 8 } }, // psllw + pand.
694 { ISD::SRL, MVT::v64i8, { 4, 8, 7,10 } }, // psrlw + pand.
695 { ISD::SRA, MVT::v64i8, { 5,10,10,15 } }, // psrlw, pand, pxor, psubb.
697 { ISD::SHL, MVT::v32i16, { 2, 4, 2, 3 } }, // psllw
698 { ISD::SRL, MVT::v32i16, { 2, 4, 2, 3 } }, // psrlw
699 { ISD::SRA, MVT::v32i16, { 2, 4, 2, 3 } }, // psrqw
704 CostTableLookup(AVX512BWUniformCostTable, ISD, LT.second))
709 { ISD::SHL, MVT::v32i16, { 5,10, 5, 7 } }, // psllw + split.
710 { ISD::SRL, MVT::v32i16, { 5,10, 5, 7 } }, // psrlw + split.
711 { ISD::SRA, MVT::v32i16, { 5,10, 5, 7 } }, // psraw + split.
713 { ISD::SHL, MVT::v16i32, { 2, 4, 2, 3 } }, // pslld
714 { ISD::SRL, MVT::v16i32, { 2, 4, 2, 3 } }, // psrld
715 { ISD::SRA, MVT::v16i32, { 2, 4, 2, 3 } }, // psrad
717 { ISD::SRA, MVT::v2i64, { 1, 2, 1, 2 } }, // psraq
718 { ISD::SHL, MVT::v4i64, { 1, 4, 1, 2 } }, // psllq
719 { ISD::SRL, MVT::v4i64, { 1, 4, 1, 2 } }, // psrlq
720 { ISD::SRA, MVT::v4i64, { 1, 4, 1, 2 } }, // psraq
721 { ISD::SHL, MVT::v8i64, { 1, 4, 1, 2 } }, // psllq
722 { ISD::SRL, MVT::v8i64, { 1, 4, 1, 2 } }, // psrlq
723 { ISD::SRA, MVT::v8i64, { 1, 4, 1, 2 } }, // psraq
728 CostTableLookup(AVX512UniformCostTable, ISD, LT.second))
734 { ISD::SHL, MVT::v16i8, { 3, 5, 5, 7 } }, // psllw + pand.
735 { ISD::SRL, MVT::v16i8, { 3, 9, 5, 8 } }, // psrlw + pand.
736 { ISD::SRA, MVT::v16i8, { 4, 5, 9,13 } }, // psrlw, pand, pxor, psubb.
737 { ISD::SHL, MVT::v32i8, { 4, 7, 6, 8 } }, // psllw + pand.
738 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand.
739 { ISD::SRA, MVT::v32i8, { 6, 9,11,16 } }, // psrlw, pand, pxor, psubb.
741 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 2 } }, // psllw.
742 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 2 } }, // psrlw.
743 { ISD::SRA, MVT::v8i16, { 1, 2, 1, 2 } }, // psraw.
744 { ISD::SHL, MVT::v16i16, { 2, 4, 2, 3 } }, // psllw.
745 { ISD::SRL, MVT::v16i16, { 2, 4, 2, 3 } }, // psrlw.
746 { ISD::SRA, MVT::v16i16, { 2, 4, 2, 3 } }, // psraw.
748 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 2 } }, // pslld
749 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 2 } }, // psrld
750 { ISD::SRA, MVT::v4i32, { 1, 2, 1, 2 } }, // psrad
751 { ISD::SHL, MVT::v8i32, { 2, 4, 2, 3 } }, // pslld
752 { ISD::SRL, MVT::v8i32, { 2, 4, 2, 3 } }, // psrld
753 { ISD::SRA, MVT::v8i32, { 2, 4, 2, 3 } }, // psrad
755 { ISD::SHL, MVT::v2i64, { 1, 2, 1, 2 } }, // psllq
756 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 2 } }, // psrlq
757 { ISD::SRA, MVT::v2i64, { 2, 4, 5, 7 } }, // 2 x psrad + shuffle.
758 { ISD::SHL, MVT::v4i64, { 2, 4, 1, 2 } }, // psllq
759 { ISD::SRL, MVT::v4i64, { 2, 4, 1, 2 } }, // psrlq
760 { ISD::SRA, MVT::v4i64, { 4, 6, 5, 9 } }, // 2 x psrad + shuffle.
765 CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
770 { ISD::SHL, MVT::v16i8, { 4, 4, 6, 8 } }, // psllw + pand.
771 { ISD::SRL, MVT::v16i8, { 4, 8, 5, 8 } }, // psrlw + pand.
772 { ISD::SRA, MVT::v16i8, { 6, 6, 9,13 } }, // psrlw, pand, pxor, psubb.
773 { ISD::SHL, MVT::v32i8, { 7, 8,11,14 } }, // psllw + pand + split.
774 { ISD::SRL, MVT::v32i8, { 7, 9,10,14 } }, // psrlw + pand + split.
775 { ISD::SRA, MVT::v32i8, { 10,11,16,21 } }, // psrlw, pand, pxor, psubb + split.
777 { ISD::SHL, MVT::v8i16, { 1, 3, 1, 2 } }, // psllw.
778 { ISD::SRL, MVT::v8i16, { 1, 3, 1, 2 } }, // psrlw.
779 { ISD::SRA, MVT::v8i16, { 1, 3, 1, 2 } }, // psraw.
780 { ISD::SHL, MVT::v16i16, { 3, 7, 5, 7 } }, // psllw + split.
781 { ISD::SRL, MVT::v16i16, { 3, 7, 5, 7 } }, // psrlw + split.
782 { ISD::SRA, MVT::v16i16, { 3, 7, 5, 7 } }, // psraw + split.
784 { ISD::SHL, MVT::v4i32, { 1, 3, 1, 2 } }, // pslld.
785 { ISD::SRL, MVT::v4i32, { 1, 3, 1, 2 } }, // psrld.
786 { ISD::SRA, MVT::v4i32, { 1, 3, 1, 2 } }, // psrad.
787 { ISD::SHL, MVT::v8i32, { 3, 7, 5, 7 } }, // pslld + split.
788 { ISD::SRL, MVT::v8i32, { 3, 7, 5, 7 } }, // psrld + split.
789 { ISD::SRA, MVT::v8i32, { 3, 7, 5, 7 } }, // psrad + split.
791 { ISD::SHL, MVT::v2i64, { 1, 3, 1, 2 } }, // psllq.
792 { ISD::SRL, MVT::v2i64, { 1, 3, 1, 2 } }, // psrlq.
793 { ISD::SRA, MVT::v2i64, { 3, 4, 5, 7 } }, // 2 x psrad + shuffle.
794 { ISD::SHL, MVT::v4i64, { 3, 7, 4, 6 } }, // psllq + split.
795 { ISD::SRL, MVT::v4i64, { 3, 7, 4, 6 } }, // psrlq + split.
796 { ISD::SRA, MVT::v4i64, { 6, 7,10,13 } }, // 2 x (2 x psrad + shuffle) + split.
803 CostTableLookup(AVXUniformCostTable, ISD, LT.second))
809 { ISD::SHL, MVT::v16i8, { 9, 10, 6, 9 } }, // psllw + pand.
810 { ISD::SRL, MVT::v16i8, { 9, 13, 5, 9 } }, // psrlw + pand.
811 { ISD::SRA, MVT::v16i8, { 11, 15, 9,13 } }, // pcmpgtb sequence.
813 { ISD::SHL, MVT::v8i16, { 2, 2, 1, 2 } }, // psllw.
814 { ISD::SRL, MVT::v8i16, { 2, 2, 1, 2 } }, // psrlw.
815 { ISD::SRA, MVT::v8i16, { 2, 2, 1, 2 } }, // psraw.
817 { ISD::SHL, MVT::v4i32, { 2, 2, 1, 2 } }, // pslld
818 { ISD::SRL, MVT::v4i32, { 2, 2, 1, 2 } }, // psrld.
819 { ISD::SRA, MVT::v4i32, { 2, 2, 1, 2 } }, // psrad.
821 { ISD::SHL, MVT::v2i64, { 2, 2, 1, 2 } }, // psllq.
822 { ISD::SRL, MVT::v2i64, { 2, 2, 1, 2 } }, // psrlq.
823 { ISD::SRA, MVT::v2i64, { 5, 9, 5, 7 } }, // 2*psrlq + xor + sub.
829 CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
834 { ISD::MUL, MVT::v2i64, { 2, 15, 1, 3 } }, // pmullq
835 { ISD::MUL, MVT::v4i64, { 2, 15, 1, 3 } }, // pmullq
836 { ISD::MUL, MVT::v8i64, { 3, 15, 1, 3 } } // pmullq
841 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
846 { ISD::SHL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsllvw/pack sequence.
847 { ISD::SRL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsrlvw/pack sequence.
848 { ISD::SRA, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsravw/pack sequence.
849 { ISD::SHL, MVT::v32i8, { 4, 23,11,16 } }, // extend/vpsllvw/pack sequence.
850 { ISD::SRL, MVT::v32i8, { 4, 30,12,18 } }, // extend/vpsrlvw/pack sequence.
851 { ISD::SRA, MVT::v32i8, { 6, 13,24,30 } }, // extend/vpsravw/pack sequence.
852 { ISD::SHL, MVT::v64i8, { 6, 19,13,15 } }, // extend/vpsllvw/pack sequence.
853 { ISD::SRL, MVT::v64i8, { 7, 27,15,18 } }, // extend/vpsrlvw/pack sequence.
854 { ISD::SRA, MVT::v64i8, { 15, 15,30,30 } }, // extend/vpsravw/pack sequence.
856 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsllvw
857 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsrlvw
858 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsravw
859 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsllvw
860 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsrlvw
861 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsravw
862 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsllvw
863 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsrlvw
864 { ISD::SRA, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsravw
866 { ISD::ADD, MVT::v64i8, { 1, 1, 1, 1 } }, // paddb
867 { ISD::ADD, MVT::v32i16, { 1, 1, 1, 1 } }, // paddw
869 { ISD::ADD, MVT::v32i8, { 1, 1, 1, 1 } }, // paddb
870 { ISD::ADD, MVT::v16i16, { 1, 1, 1, 1 } }, // paddw
871 { ISD::ADD, MVT::v8i32, { 1, 1, 1, 1 } }, // paddd
872 { ISD::ADD, MVT::v4i64, { 1, 1, 1, 1 } }, // paddq
874 { ISD::SUB, MVT::v64i8, { 1, 1, 1, 1 } }, // psubb
875 { ISD::SUB, MVT::v32i16, { 1, 1, 1, 1 } }, // psubw
877 { ISD::MUL, MVT::v16i8, { 4, 12, 4, 5 } }, // extend/pmullw/trunc
878 { ISD::MUL, MVT::v32i8, { 3, 10, 7,10 } }, // pmaddubsw
879 { ISD::MUL, MVT::v64i8, { 3, 11, 7,10 } }, // pmaddubsw
880 { ISD::MUL, MVT::v32i16, { 1, 5, 1, 1 } }, // pmullw
882 { ISD::SUB, MVT::v32i8, { 1, 1, 1, 1 } }, // psubb
883 { ISD::SUB, MVT::v16i16, { 1, 1, 1, 1 } }, // psubw
884 { ISD::SUB, MVT::v8i32, { 1, 1, 1, 1 } }, // psubd
885 { ISD::SUB, MVT::v4i64, { 1, 1, 1, 1 } }, // psubq
890 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
895 { ISD::SHL, MVT::v64i8, { 15, 19,27,33 } }, // vpblendv+split sequence.
896 { ISD::SRL, MVT::v64i8, { 15, 19,30,36 } }, // vpblendv+split sequence.
897 { ISD::SRA, MVT::v64i8, { 37, 37,51,63 } }, // vpblendv+split sequence.
899 { ISD::SHL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence.
900 { ISD::SRL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence.
901 { ISD::SRA, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsravd/pack sequence.
903 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } },
904 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } },
905 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } },
906 { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } },
907 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } },
908 { ISD::SRA, MVT::v8i32, { 1, 1, 1, 1 } },
909 { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } },
910 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } },
911 { ISD::SRA, MVT::v16i32, { 1, 1, 1, 1 } },
913 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } },
914 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } },
915 { ISD::SRA, MVT::v2i64, { 1, 1, 1, 1 } },
916 { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } },
917 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } },
918 { ISD::SRA, MVT::v4i64, { 1, 1, 1, 1 } },
919 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } },
920 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } },
921 { ISD::SRA, MVT::v8i64, { 1, 1, 1, 1 } },
923 { ISD::ADD, MVT::v64i8, { 3, 7, 5, 5 } }, // 2*paddb + split
924 { ISD::ADD, MVT::v32i16, { 3, 7, 5, 5 } }, // 2*paddw + split
926 { ISD::SUB, MVT::v64i8, { 3, 7, 5, 5 } }, // 2*psubb + split
927 { ISD::SUB, MVT::v32i16, { 3, 7, 5, 5 } }, // 2*psubw + split
929 { ISD::AND, MVT::v32i8, { 1, 1, 1, 1 } },
930 { ISD::AND, MVT::v16i16, { 1, 1, 1, 1 } },
931 { ISD::AND, MVT::v8i32, { 1, 1, 1, 1 } },
932 { ISD::AND, MVT::v4i64, { 1, 1, 1, 1 } },
934 { ISD::OR, MVT::v32i8, { 1, 1, 1, 1 } },
935 { ISD::OR, MVT::v16i16, { 1, 1, 1, 1 } },
936 { ISD::OR, MVT::v8i32, { 1, 1, 1, 1 } },
937 { ISD::OR, MVT::v4i64, { 1, 1, 1, 1 } },
939 { ISD::XOR, MVT::v32i8, { 1, 1, 1, 1 } },
940 { ISD::XOR, MVT::v16i16, { 1, 1, 1, 1 } },
941 { ISD::XOR, MVT::v8i32, { 1, 1, 1, 1 } },
942 { ISD::XOR, MVT::v4i64, { 1, 1, 1, 1 } },
944 { ISD::MUL, MVT::v16i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
945 { ISD::MUL, MVT::v8i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
946 { ISD::MUL, MVT::v4i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
947 { ISD::MUL, MVT::v8i64, { 6, 9, 8, 8 } }, // 3*pmuludq/3*shift/2*add
948 { ISD::MUL, MVT::i64, { 1 } }, // Skylake from http://www.agner.org/
952 { ISD::FNEG, MVT::v8f64, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/
953 { ISD::FADD, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
954 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
955 { ISD::FSUB, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
956 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
957 { ISD::FMUL, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
958 { ISD::FMUL, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
959 { ISD::FMUL, MVT::v2f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
960 { ISD::FMUL, MVT::f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
962 { ISD::FDIV, MVT::f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/
963 { ISD::FDIV, MVT::v2f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/
964 { ISD::FDIV, MVT::v4f64, { 8, 14, 1, 1 } }, // Skylake from http://www.agner.org/
965 { ISD::FDIV, MVT::v8f64, { 16, 23, 1, 3 } }, // Skylake from http://www.agner.org/
967 { ISD::FNEG, MVT::v16f32, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/
968 { ISD::FADD, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
969 { ISD::FADD, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
970 { ISD::FSUB, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
971 { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
972 { ISD::FMUL, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
973 { ISD::FMUL, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
974 { ISD::FMUL, MVT::v4f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
975 { ISD::FMUL, MVT::f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
977 { ISD::FDIV, MVT::f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/
978 { ISD::FDIV, MVT::v4f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/
979 { ISD::FDIV, MVT::v8f32, { 5, 11, 1, 1 } }, // Skylake from http://www.agner.org/
980 { ISD::FDIV, MVT::v16f32, { 10, 18, 1, 3 } }, // Skylake from http://www.agner.org/
984 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
991 { ISD::SHL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsllvd (Haswell from agner.org)
992 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsrlvd (Haswell from agner.org)
993 { ISD::SRA, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsravd (Haswell from agner.org)
994 { ISD::SHL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsllvd (Haswell from agner.org)
995 { ISD::SRL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsrlvd (Haswell from agner.org)
996 { ISD::SRA, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsravd (Haswell from agner.org)
997 { ISD::SHL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsllvq (Haswell from agner.org)
998 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsrlvq (Haswell from agner.org)
999 { ISD::SHL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsllvq (Haswell from agner.org)
1000 { ISD::SRL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsrlvq (Haswell from agner.org)
1004 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && Op2Info.isConstant())
1013 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
1020 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
1027 { ISD::SHL, MVT::v16i8, { 1, 3, 1, 1 } },
1028 { ISD::SRL, MVT::v16i8, { 2, 3, 1, 1 } },
1029 { ISD::SRA, MVT::v16i8, { 2, 3, 1, 1 } },
1030 { ISD::SHL, MVT::v8i16, { 1, 3, 1, 1 } },
1031 { ISD::SRL, MVT::v8i16, { 2, 3, 1, 1 } },
1032 { ISD::SRA, MVT::v8i16, { 2, 3, 1, 1 } },
1033 { ISD::SHL, MVT::v4i32, { 1, 3, 1, 1 } },
1034 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 1 } },
1035 { ISD::SRA, MVT::v4i32, { 2, 3, 1, 1 } },
1036 { ISD::SHL, MVT::v2i64, { 1, 3, 1, 1 } },
1037 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } },
1038 { ISD::SRA, MVT::v2i64, { 2, 3, 1, 1 } },
1040 { ISD::SHL, MVT::v32i8, { 4, 7, 5, 6 } },
1041 { ISD::SRL, MVT::v32i8, { 6, 7, 5, 6 } },
1042 { ISD::SRA, MVT::v32i8, { 6, 7, 5, 6 } },
1043 { ISD::SHL, MVT::v16i16, { 4, 7, 5, 6 } },
1044 { ISD::SRL, MVT::v16i16, { 6, 7, 5, 6 } },
1045 { ISD::SRA, MVT::v16i16, { 6, 7, 5, 6 } },
1046 { ISD::SHL, MVT::v8i32, { 4, 7, 5, 6 } },
1047 { ISD::SRL, MVT::v8i32, { 6, 7, 5, 6 } },
1048 { ISD::SRA, MVT::v8i32, { 6, 7, 5, 6 } },
1049 { ISD::SHL, MVT::v4i64, { 4, 7, 5, 6 } },
1050 { ISD::SRL, MVT::v4i64, { 6, 7, 5, 6 } },
1051 { ISD::SRA, MVT::v4i64, { 6, 7, 5, 6 } },
1058 int ShiftISD = ISD;
1059 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && Op2Info.isConstant())
1060 ShiftISD = ISD::SHL;
1067 if (ISD == ISD::SHL && !Op2Info.isUniform() && Op2Info.isConstant()) {
1073 ISD = ISD::MUL;
1077 { ISD::FDIV, MVT::f32, { 18, 19, 1, 1 } }, // divss
1078 { ISD::FDIV, MVT::v4f32, { 35, 36, 1, 1 } }, // divps
1079 { ISD::FDIV, MVT::f64, { 33, 34, 1, 1 } }, // divsd
1080 { ISD::FDIV, MVT::v2f64, { 65, 66, 1, 1 } }, // divpd
1084 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, LT.second))
1089 { ISD::MUL, MVT::v4i32, { 11, 11, 1, 7 } }, // pmulld
1090 { ISD::MUL, MVT::v8i16, { 2, 5, 1, 1 } }, // pmullw
1091 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // mulsd
1092 { ISD::FMUL, MVT::f32, { 1, 4, 1, 1 } }, // mulss
1093 { ISD::FMUL, MVT::v2f64, { 4, 7, 1, 1 } }, // mulpd
1094 { ISD::FMUL, MVT::v4f32, { 2, 5, 1, 1 } }, // mulps
1095 { ISD::FDIV, MVT::f32, { 17, 19, 1, 1 } }, // divss
1096 { ISD::FDIV, MVT::v4f32, { 39, 39, 1, 6 } }, // divps
1097 { ISD::FDIV, MVT::f64, { 32, 34, 1, 1 } }, // divsd
1098 { ISD::FDIV, MVT::v2f64, { 69, 69, 1, 6 } }, // divpd
1099 { ISD::FADD, MVT::v2f64, { 2, 4, 1, 1 } }, // addpd
1100 { ISD::FSUB, MVT::v2f64, { 2, 4, 1, 1 } }, // subpd
1106 { ISD::MUL, MVT::v2i64, { 17, 22, 9, 9 } },
1108 { ISD::ADD, MVT::v2i64, { 4, 2, 1, 2 } },
1109 { ISD::SUB, MVT::v2i64, { 4, 2, 1, 2 } },
1113 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, LT.second))
1118 { ISD::SHL, MVT::v16i8, { 6, 21,11,16 } }, // vpblendvb sequence.
1119 { ISD::SHL, MVT::v32i8, { 6, 23,11,22 } }, // vpblendvb sequence.
1120 { ISD::SHL, MVT::v8i16, { 5, 18, 5,10 } }, // extend/vpsrlvd/pack sequence.
1121 { ISD::SHL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence.
1123 { ISD::SRL, MVT::v16i8, { 6, 27,12,18 } }, // vpblendvb sequence.
1124 { ISD::SRL, MVT::v32i8, { 8, 30,12,24 } }, // vpblendvb sequence.
1125 { ISD::SRL, MVT::v8i16, { 5, 11, 5,10 } }, // extend/vpsrlvd/pack sequence.
1126 { ISD::SRL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence.
1128 { ISD::SRA, MVT::v16i8, { 17, 17,24,30 } }, // vpblendvb sequence.
1129 { ISD::SRA, MVT::v32i8, { 18, 20,24,43 } }, // vpblendvb sequence.
1130 { ISD::SRA, MVT::v8i16, { 5, 11, 5,10 } }, // extend/vpsravd/pack sequence.
1131 { ISD::SRA, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsravd/pack sequence.
1132 { ISD::SRA, MVT::v2i64, { 4, 5, 5, 5 } }, // srl/xor/sub sequence.
1133 { ISD::SRA, MVT::v4i64, { 8, 8, 5, 9 } }, // srl/xor/sub sequence.
1135 { ISD::SUB, MVT::v32i8, { 1, 1, 1, 2 } }, // psubb
1136 { ISD::ADD, MVT::v32i8, { 1, 1, 1, 2 } }, // paddb
1137 { ISD::SUB, MVT::v16i16, { 1, 1, 1, 2 } }, // psubw
1138 { ISD::ADD, MVT::v16i16, { 1, 1, 1, 2 } }, // paddw
1139 { ISD::SUB, MVT::v8i32, { 1, 1, 1, 2 } }, // psubd
1140 { ISD::ADD, MVT::v8i32, { 1, 1, 1, 2 } }, // paddd
1141 { ISD::SUB, MVT::v4i64, { 1, 1, 1, 2 } }, // psubq
1142 { ISD::ADD, MVT::v4i64, { 1, 1, 1, 2 } }, // paddq
1144 { ISD::MUL, MVT::v16i8, { 5, 18, 6,12 } }, // extend/pmullw/pack
1145 { ISD::MUL, MVT::v32i8, { 4, 8, 8,16 } }, // pmaddubsw
1146 { ISD::MUL, MVT::v16i16, { 2, 5, 1, 2 } }, // pmullw
1147 { ISD::MUL, MVT::v8i32, { 4, 10, 1, 2 } }, // pmulld
1148 { ISD::MUL, MVT::v4i32, { 2, 10, 1, 2 } }, // pmulld
1149 { ISD::MUL, MVT::v4i64, { 6, 10, 8,13 } }, // 3*pmuludq/3*shift/2*add
1150 { ISD::MUL, MVT::v2i64, { 6, 10, 8, 8 } }, // 3*pmuludq/3*shift/2*add
1154 { ISD::FNEG, MVT::v4f64, { 1, 1, 1, 2 } }, // vxorpd
1155 { ISD::FNEG, MVT::v8f32, { 1, 1, 1, 2 } }, // vxorps
1157 { ISD::FADD, MVT::f64, { 1, 4, 1, 1 } }, // vaddsd
1158 { ISD::FADD, MVT::f32, { 1, 4, 1, 1 } }, // vaddss
1159 { ISD::FADD, MVT::v2f64, { 1, 4, 1, 1 } }, // vaddpd
1160 { ISD::FADD, MVT::v4f32, { 1, 4, 1, 1 } }, // vaddps
1161 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 2 } }, // vaddpd
1162 { ISD::FADD, MVT::v8f32, { 1, 4, 1, 2 } }, // vaddps
1164 { ISD::FSUB, MVT::f64, { 1, 4, 1, 1 } }, // vsubsd
1165 { ISD::FSUB, MVT::f32, { 1, 4, 1, 1 } }, // vsubss
1166 { ISD::FSUB, MVT::v2f64, { 1, 4, 1, 1 } }, // vsubpd
1167 { ISD::FSUB, MVT::v4f32, { 1, 4, 1, 1 } }, // vsubps
1168 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 2 } }, // vsubpd
1169 { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 2 } }, // vsubps
1171 { ISD::FMUL, MVT::f64, { 1, 5, 1, 1 } }, // vmulsd
1172 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // vmulss
1173 { ISD::FMUL, MVT::v2f64, { 1, 5, 1, 1 } }, // vmulpd
1174 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // vmulps
1175 { ISD::FMUL, MVT::v4f64, { 1, 5, 1, 2 } }, // vmulpd
1176 { ISD::FMUL, MVT::v8f32, { 1, 5, 1, 2 } }, // vmulps
1178 { ISD::FDIV, MVT::f32, { 7, 13, 1, 1 } }, // vdivss
1179 { ISD::FDIV, MVT::v4f32, { 7, 13, 1, 1 } }, // vdivps
1180 { ISD::FDIV, MVT::v8f32, { 14, 21, 1, 3 } }, // vdivps
1181 { ISD::FDIV, MVT::f64, { 14, 20, 1, 1 } }, // vdivsd
1182 { ISD::FDIV, MVT::v2f64, { 14, 20, 1, 1 } }, // vdivpd
1183 { ISD::FDIV, MVT::v4f64, { 28, 35, 1, 3 } }, // vdivpd
1188 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
1196 { ISD::MUL, MVT::v32i8, { 10, 11, 18, 19 } }, // pmaddubsw + split
1197 { ISD::MUL, MVT::v16i8, { 5, 6, 8, 12 } }, // 2*pmaddubsw/3*and/psllw/or
1198 { ISD::MUL, MVT::v16i16, { 4, 8, 5, 6 } }, // pmullw + split
1199 { ISD::MUL, MVT::v8i32, { 5, 8, 5, 10 } }, // pmulld + split
1200 { ISD::MUL, MVT::v4i32, { 2, 5, 1, 3 } }, // pmulld
1201 { ISD::MUL, MVT::v4i64, { 12, 15, 19, 20 } },
1203 { ISD::AND, MVT::v32i8, { 1, 1, 1, 2 } }, // vandps
1204 { ISD::AND, MVT::v16i16, { 1, 1, 1, 2 } }, // vandps
1205 { ISD::AND, MVT::v8i32, { 1, 1, 1, 2 } }, // vandps
1206 { ISD::AND, MVT::v4i64, { 1, 1, 1, 2 } }, // vandps
1208 { ISD::OR, MVT::v32i8, { 1, 1, 1, 2 } }, // vorps
1209 { ISD::OR, MVT::v16i16, { 1, 1, 1, 2 } }, // vorps
1210 { ISD::OR, MVT::v8i32, { 1, 1, 1, 2 } }, // vorps
1211 { ISD::OR, MVT::v4i64, { 1, 1, 1, 2 } }, // vorps
1213 { ISD::XOR, MVT::v32i8, { 1, 1, 1, 2 } }, // vxorps
1214 { ISD::XOR, MVT::v16i16, { 1, 1, 1, 2 } }, // vxorps
1215 { ISD::XOR, MVT::v8i32, { 1, 1, 1, 2 } }, // vxorps
1216 { ISD::XOR, MVT::v4i64, { 1, 1, 1, 2 } }, // vxorps
1218 { ISD::SUB, MVT::v32i8, { 4, 2, 5, 6 } }, // psubb + split
1219 { ISD::ADD, MVT::v32i8, { 4, 2, 5, 6 } }, // paddb + split
1220 { ISD::SUB, MVT::v16i16, { 4, 2, 5, 6 } }, // psubw + split
1221 { ISD::ADD, MVT::v16i16, { 4, 2, 5, 6 } }, // paddw + split
1222 { ISD::SUB, MVT::v8i32, { 4, 2, 5, 6 } }, // psubd + split
1223 { ISD::ADD, MVT::v8i32, { 4, 2, 5, 6 } }, // paddd + split
1224 { ISD::SUB, MVT::v4i64, { 4, 2, 5, 6 } }, // psubq + split
1225 { ISD::ADD, MVT::v4i64, { 4, 2, 5, 6 } }, // paddq + split
1226 { ISD::SUB, MVT::v2i64, { 1, 1, 1, 1 } }, // psubq
1227 { ISD::ADD, MVT::v2i64, { 1, 1, 1, 1 } }, // paddq
1229 { ISD::SHL, MVT::v16i8, { 10, 21,11,17 } }, // pblendvb sequence.
1230 { ISD::SHL, MVT::v32i8, { 22, 22,27,40 } }, // pblendvb sequence + split.
1231 { ISD::SHL, MVT::v8i16, { 6, 9,11,11 } }, // pblendvb sequence.
1232 { ISD::SHL, MVT::v16i16, { 13, 16,24,25 } }, // pblendvb sequence + split.
1233 { ISD::SHL, MVT::v4i32, { 3, 11, 4, 6 } }, // pslld/paddd/cvttps2dq/pmulld
1234 { ISD::SHL, MVT::v8i32, { 9, 11,12,17 } }, // pslld/paddd/cvttps2dq/pmulld + split
1235 { ISD::SHL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend.
1236 { ISD::SHL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split.
1238 { ISD::SRL, MVT::v16i8, { 11, 27,12,18 } }, // pblendvb sequence.
1239 { ISD::SRL, MVT::v32i8, { 23, 23,30,43 } }, // pblendvb sequence + split.
1240 { ISD::SRL, MVT::v8i16, { 13, 16,14,22 } }, // pblendvb sequence.
1241 { ISD::SRL, MVT::v16i16, { 28, 30,31,48 } }, // pblendvb sequence + split.
1242 { ISD::SRL, MVT::v4i32, { 6, 7,12,16 } }, // Shift each lane + blend.
1243 { ISD::SRL, MVT::v8i32, { 14, 14,26,34 } }, // Shift each lane + blend + split.
1244 { ISD::SRL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend.
1245 { ISD::SRL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split.
1247 { ISD::SRA, MVT::v16i8, { 21, 22,24,36 } }, // pblendvb sequence.
1248 { ISD::SRA, MVT::v32i8, { 44, 45,51,76 } }, // pblendvb sequence + split.
1249 { ISD::SRA, MVT::v8i16, { 13, 16,14,22 } }, // pblendvb sequence.
1250 { ISD::SRA, MVT::v16i16, { 28, 30,31,48 } }, // pblendvb sequence + split.
1251 { ISD::SRA, MVT::v4i32, { 6, 7,12,16 } }, // Shift each lane + blend.
1252 { ISD::SRA, MVT::v8i32, { 14, 14,26,34 } }, // Shift each lane + blend + split.
1253 { ISD::SRA, MVT::v2i64, { 5, 6,10,14 } }, // Shift each lane + blend.
1254 { ISD::SRA, MVT::v4i64, { 12, 12,22,30 } }, // Shift each lane + blend + split.
1256 { ISD::FNEG, MVT::v4f64, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/
1257 { ISD::FNEG, MVT::v8f32, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/
1259 { ISD::FADD, MVT::f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1260 { ISD::FADD, MVT::f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1261 { ISD::FADD, MVT::v2f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1262 { ISD::FADD, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1263 { ISD::FADD, MVT::v4f64, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1264 { ISD::FADD, MVT::v8f32, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1266 { ISD::FSUB, MVT::f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1267 { ISD::FSUB, MVT::f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1268 { ISD::FSUB, MVT::v2f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1269 { ISD::FSUB, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1270 { ISD::FSUB, MVT::v4f64, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1271 { ISD::FSUB, MVT::v8f32, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1273 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1274 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1275 { ISD::FMUL, MVT::v2f64, { 2, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1276 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1277 { ISD::FMUL, MVT::v4f64, { 4, 5, 1, 2 } }, // BTVER2 from http://www.agner.org/
1278 { ISD::FMUL, MVT::v8f32, { 2, 5, 1, 2 } }, // BTVER2 from http://www.agner.org/
1280 { ISD::FDIV, MVT::f32, { 14, 14, 1, 1 } }, // SNB from http://www.agner.org/
1281 { ISD::FDIV, MVT::v4f32, { 14, 14, 1, 1 } }, // SNB from http://www.agner.org/
1282 { ISD::FDIV, MVT::v8f32, { 28, 29, 1, 3 } }, // SNB from http://www.agner.org/
1283 { ISD::FDIV, MVT::f64, { 22, 22, 1, 1 } }, // SNB from http://www.agner.org/
1284 { ISD::FDIV, MVT::v2f64, { 22, 22, 1, 1 } }, // SNB from http://www.agner.org/
1285 { ISD::FDIV, MVT::v4f64, { 44, 45, 1, 3 } }, // SNB from http://www.agner.org/
1289 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
1294 { ISD::FADD, MVT::f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1295 { ISD::FADD, MVT::f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1296 { ISD::FADD, MVT::v2f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1297 { ISD::FADD, MVT::v4f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1299 { ISD::FSUB, MVT::f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1300 { ISD::FSUB, MVT::f32 , { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1301 { ISD::FSUB, MVT::v2f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1302 { ISD::FSUB, MVT::v4f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1304 { ISD::FMUL, MVT::f64, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1305 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1306 { ISD::FMUL, MVT::v2f64, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1307 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1309 { ISD::FDIV, MVT::f32, { 14, 14, 1, 1 } }, // Nehalem from http://www.agner.org/
1310 { ISD::FDIV, MVT::v4f32, { 14, 14, 1, 1 } }, // Nehalem from http://www.agner.org/
1311 { ISD::FDIV, MVT::f64, { 22, 22, 1, 1 } }, // Nehalem from http://www.agner.org/
1312 { ISD::FDIV, MVT::v2f64, { 22, 22, 1, 1 } }, // Nehalem from http://www.agner.org/
1314 { ISD::MUL, MVT::v2i64, { 6, 10,10,10 } } // 3*pmuludq/3*shift/2*add
1318 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
1323 { ISD::SHL, MVT::v16i8, { 15, 24,17,22 } }, // pblendvb sequence.
1324 { ISD::SHL, MVT::v8i16, { 11, 14,11,11 } }, // pblendvb sequence.
1325 { ISD::SHL, MVT::v4i32, { 14, 20, 4,10 } }, // pslld/paddd/cvttps2dq/pmulld
1327 { ISD::SRL, MVT::v16i8, { 16, 27,18,24 } }, // pblendvb sequence.
1328 { ISD::SRL, MVT::v8i16, { 22, 26,23,27 } }, // pblendvb sequence.
1329 { ISD::SRL, MVT::v4i32, { 16, 17,15,19 } }, // Shift each lane + blend.
1330 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1332 { ISD::SRA, MVT::v16i8, { 38, 41,30,36 } }, // pblendvb sequence.
1333 { ISD::SRA, MVT::v8i16, { 22, 26,23,27 } }, // pblendvb sequence.
1334 { ISD::SRA, MVT::v4i32, { 16, 17,15,19 } }, // Shift each lane + blend.
1335 { ISD::SRA, MVT::v2i64, { 8, 17, 5, 7 } }, // splat+shuffle sequence.
1337 { ISD::MUL, MVT::v4i32, { 2, 11, 1, 1 } } // pmulld (Nehalem from agner.org)
1341 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
1346 { ISD::MUL, MVT::v16i8, { 5, 18,10,12 } }, // 2*pmaddubsw/3*and/psllw/or
1350 if (const auto *Entry = CostTableLookup(SSSE3CostTable, ISD, LT.second))
1357 { ISD::SHL, MVT::v16i8, { 13, 21,26,28 } }, // cmpgtb sequence.
1358 { ISD::SHL, MVT::v8i16, { 24, 27,16,20 } }, // cmpgtw sequence.
1359 { ISD::SHL, MVT::v4i32, { 17, 19,10,12 } }, // pslld/paddd/cvttps2dq/pmuludq.
1360 { ISD::SHL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1362 { ISD::SRL, MVT::v16i8, { 14, 28,27,30 } }, // cmpgtb sequence.
1363 { ISD::SRL, MVT::v8i16, { 16, 19,31,31 } }, // cmpgtw sequence.
1364 { ISD::SRL, MVT::v4i32, { 12, 12,15,19 } }, // Shift each lane + blend.
1365 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1367 { ISD::SRA, MVT::v16i8, { 27, 30,54,54 } }, // unpacked cmpgtb sequence.
1368 { ISD::SRA, MVT::v8i16, { 16, 19,31,31 } }, // cmpgtw sequence.
1369 { ISD::SRA, MVT::v4i32, { 12, 12,15,19 } }, // Shift each lane + blend.
1370 { ISD::SRA, MVT::v2i64, { 8, 11,12,16 } }, // srl/xor/sub splat+shuffle sequence.
1372 { ISD::AND, MVT::v16i8, { 1, 1, 1, 1 } }, // pand
1373 { ISD::AND, MVT::v8i16, { 1, 1, 1, 1 } }, // pand
1374 { ISD::AND, MVT::v4i32, { 1, 1, 1, 1 } }, // pand
1375 { ISD::AND, MVT::v2i64, { 1, 1, 1, 1 } }, // pand
1377 { ISD::OR, MVT::v16i8, { 1, 1, 1, 1 } }, // por
1378 { ISD::OR, MVT::v8i16, { 1, 1, 1, 1 } }, // por
1379 { ISD::OR, MVT::v4i32, { 1, 1, 1, 1 } }, // por
1380 { ISD::OR, MVT::v2i64, { 1, 1, 1, 1 } }, // por
1382 { ISD::XOR, MVT::v16i8, { 1, 1, 1, 1 } }, // pxor
1383 { ISD::XOR, MVT::v8i16, { 1, 1, 1, 1 } }, // pxor
1384 { ISD::XOR, MVT::v4i32, { 1, 1, 1, 1 } }, // pxor
1385 { ISD::XOR, MVT::v2i64, { 1, 1, 1, 1 } }, // pxor
1387 { ISD::ADD, MVT::v2i64, { 1, 2, 1, 2 } }, // paddq
1388 { ISD::SUB, MVT::v2i64, { 1, 2, 1, 2 } }, // psubq
1390 { ISD::MUL, MVT::v16i8, { 6, 18,12,12 } }, // 2*unpack/2*pmullw/2*and/pack
1391 { ISD::MUL, MVT::v8i16, { 1, 5, 1, 1 } }, // pmullw
1392 { ISD::MUL, MVT::v4i32, { 6, 8, 7, 7 } }, // 3*pmuludq/4*shuffle
1393 { ISD::MUL, MVT::v2i64, { 7, 10,10,10 } }, // 3*pmuludq/3*shift/2*add
1397 { ISD::FDIV, MVT::f32, { 23, 23, 1, 1 } }, // Pentium IV from http://www.agner.org/
1398 { ISD::FDIV, MVT::v4f32, { 39, 39, 1, 1 } }, // Pentium IV from http://www.agner.org/
1399 { ISD::FDIV, MVT::f64, { 38, 38, 1, 1 } }, // Pentium IV from http://www.agner.org/
1400 { ISD::FDIV, MVT::v2f64, { 69, 69, 1, 1 } }, // Pentium IV from http://www.agner.org/
1402 { ISD::FNEG, MVT::f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1403 { ISD::FNEG, MVT::f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1404 { ISD::FNEG, MVT::v4f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1405 { ISD::FNEG, MVT::v2f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1407 { ISD::FADD, MVT::f32, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1408 { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1409 { ISD::FADD, MVT::v2f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1411 { ISD::FSUB, MVT::f32, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1412 { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1413 { ISD::FSUB, MVT::v2f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1415 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // Pentium IV from http://www.agner.org/
1416 { ISD::FMUL, MVT::v2f64, { 2, 5, 1, 1 } }, // Pentium IV from http://www.agner.org/
1420 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
1425 { ISD::FDIV, MVT::f32, { 17, 18, 1, 1 } }, // Pentium III from http://www.agner.org/
1426 { ISD::FDIV, MVT::v4f32, { 34, 48, 1, 1 } }, // Pentium III from http://www.agner.org/
1428 { ISD::FNEG, MVT::f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/
1429 { ISD::FNEG, MVT::v4f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/
1431 { ISD::FADD, MVT::f32, { 1, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1432 { ISD::FADD, MVT::v4f32, { 2, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1434 { ISD::FSUB, MVT::f32, { 1, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1435 { ISD::FSUB, MVT::v4f32, { 2, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1437 { ISD::FMUL, MVT::f32, { 2, 5, 1, 1 } }, // Pentium III from http://www.agner.org/
1438 { ISD::FMUL, MVT::v4f32, { 2, 5, 1, 1 } }, // Pentium III from http://www.agner.org/
1442 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
1447 { ISD::ADD, MVT::i64, { 1 } }, // Core (Merom) from http://www.agner.org/
1448 { ISD::SUB, MVT::i64, { 1 } }, // Core (Merom) from http://www.agner.org/
1449 { ISD::MUL, MVT::i64, { 2, 6, 1, 2 } },
1453 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second))
1458 { ISD::ADD, MVT::i8, { 1 } }, // Pentium III from http://www.agner.org/
1459 { ISD::ADD, MVT::i16, { 1 } }, // Pentium III from http://www.agner.org/
1460 { ISD::ADD, MVT::i32, { 1 } }, // Pentium III from http://www.agner.org/
1462 { ISD::SUB, MVT::i8, { 1 } }, // Pentium III from http://www.agner.org/
1463 { ISD::SUB, MVT::i16, { 1 } }, // Pentium III from http://www.agner.org/
1464 { ISD::SUB, MVT::i32, { 1 } }, // Pentium III from http://www.agner.org/
1466 { ISD::MUL, MVT::i8, { 3, 4, 1, 1 } },
1467 { ISD::MUL, MVT::i16, { 2, 4, 1, 1 } },
1468 { ISD::MUL, MVT::i32, { 1, 4, 1, 1 } },
1470 { ISD::FNEG, MVT::f64, { 2, 2, 1, 3 } }, // (x87)
1471 { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // (x87)
1472 { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // (x87)
1473 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // (x87)
1474 { ISD::FDIV, MVT::f64, { 38, 38, 1, 1 } }, // (x87)
1477 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second))
1488 (ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
1489 ISD == ISD::UREM)) {
1498 switch (ISD) {
1499 case ISD::FADD:
1500 case ISD::FSUB:
1501 case ISD::FMUL:
1502 case ISD::FDIV:
1503 case ISD::FNEG:
1504 case ISD::AND:
1505 case ISD::OR:
1506 case ISD::XOR:
2175 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2176 assert(ISD && "Invalid opcode");
2184 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, { 1, 1, 1, 1 } },
2185 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, { 1, 1, 1, 1 } },
2188 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 1, 1, 1, 1 } },
2189 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, { 1, 1, 1, 1 } },
2190 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 1, 1, 1, 1 } },
2191 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, { 1, 1, 1, 1 } },
2192 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 1, 1, 1, 1 } },
2193 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, { 1, 1, 1, 1 } },
2194 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 1, 1, 1, 1 } },
2195 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, { 1, 1, 1, 1 } },
2196 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 1, 1, 1, 1 } },
2197 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, { 1, 1, 1, 1 } },
2198 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, { 1, 1, 1, 1 } },
2199 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, { 1, 1, 1, 1 } },
2200 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 1, 1, 1, 1 } },
2201 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, { 1, 1, 1, 1 } },
2202 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, { 1, 1, 1, 1 } },
2203 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, { 1, 1, 1, 1 } },
2204 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, { 1, 1, 1, 1 } },
2207 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 2, 1, 1, 1 } },
2208 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, { 2, 1, 1, 1 } },
2209 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 2, 1, 1, 1 } },
2210 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, { 2, 1, 1, 1 } },
2211 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 2, 1, 1, 1 } },
2212 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, { 2, 1, 1, 1 } },
2213 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 2, 1, 1, 1 } },
2214 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, { 2, 1, 1, 1 } },
2215 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 2, 1, 1, 1 } },
2216 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, { 2, 1, 1, 1 } },
2217 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, { 2, 1, 1, 1 } },
2218 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, { 2, 1, 1, 1 } },
2219 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 2, 1, 1, 1 } },
2220 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, { 2, 1, 1, 1 } },
2221 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, { 2, 1, 1, 1 } },
2222 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, { 2, 1, 1, 1 } },
2223 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, { 2, 1, 1, 1 } },
2225 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 2, 1, 1, 1 } },
2226 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, { 2, 1, 1, 1 } },
2227 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 2, 1, 1, 1 } },
2228 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, { 2, 1, 1, 1 } },
2229 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 2, 1, 1, 1 } },
2230 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, { 2, 1, 1, 1 } },
2231 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 2, 1, 1, 1 } },
2232 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, { 2, 1, 1, 1 } },
2233 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 2, 1, 1, 1 } },
2234 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, { 2, 1, 1, 1 } },
2235 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, { 2, 1, 1, 1 } },
2236 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, { 2, 1, 1, 1 } },
2237 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 2, 1, 1, 1 } },
2238 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, { 2, 1, 1, 1 } },
2239 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, { 2, 1, 1, 1 } },
2240 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, { 2, 1, 1, 1 } },
2241 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, { 2, 1, 1, 1 } },
2243 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, { 2, 1, 1, 1 } },
2244 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 2, 1, 1, 1 } }, // widen to zmm
2245 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, { 2, 1, 1, 1 } }, // vpmovwb
2246 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, { 2, 1, 1, 1 } }, // vpmovwb
2247 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, { 2, 1, 1, 1 } }, // vpmovwb
2252 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, { 1, 1, 1, 1 } },
2253 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, { 1, 1, 1, 1 } },
2254 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, { 1, 1, 1, 1 } },
2255 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 1, 1, 1, 1 } },
2256 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 1, 1, 1, 1 } },
2257 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, { 1, 1, 1, 1 } },
2258 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, { 1, 1, 1, 1 } },
2259 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, { 1, 1, 1, 1 } },
2262 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, { 2, 1, 1, 1, } },
2263 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, { 2, 1, 1, 1, } },
2264 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, { 2, 1, 1, 1, } },
2265 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 2, 1, 1, 1, } },
2266 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 2, 1, 1, 1, } },
2267 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, { 2, 1, 1, 1, } },
2268 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, { 2, 1, 1, 1, } },
2269 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, { 2, 1, 1, 1, } },
2271 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, { 2, 1, 1, 1 } },
2272 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, { 2, 1, 1, 1 } },
2273 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, { 2, 1, 1, 1 } },
2274 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 2, 1, 1, 1 } },
2275 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } },
2276 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, { 2, 1, 1, 1 } },
2277 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, { 2, 1, 1, 1 } },
2278 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, { 2, 1, 1, 1 } },
2280 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, { 1, 1, 1, 1 } },
2281 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, { 1, 1, 1, 1 } },
2283 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, { 1, 1, 1, 1 } },
2284 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, { 1, 1, 1, 1 } },
2286 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, { 1, 1, 1, 1 } },
2287 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, { 1, 1, 1, 1 } },
2289 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, { 1, 1, 1, 1 } },
2290 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, { 1, 1, 1, 1 } },
2297 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, { 1, 1, 1, 1 } },
2298 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, { 3, 1, 1, 1 } },
2299 { ISD::FP_EXTEND, MVT::v16f64, MVT::v16f32, { 4, 1, 1, 1 } }, // 2*vcvtps2pd+vextractf64x4
2300 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, { 1, 1, 1, 1 } },
2302 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2303 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2304 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2305 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2306 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2307 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2308 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2309 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2310 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, { 2, 1, 1, 1 } }, // zmm vpslld+vptestmd
2311 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, { 2, 1, 1, 1 } }, // zmm vpslld+vptestmd
2312 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } }, // zmm vpslld+vptestmd
2313 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2314 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, { 2, 1, 1, 1 } }, // zmm vpsllq+vptestmq
2315 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 2, 1, 1, 1 } }, // zmm vpsllq+vptestmq
2316 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, { 2, 1, 1, 1 } }, // vpsllq+vptestmq
2317 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, { 2, 1, 1, 1 } }, // vpmovdb
2318 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, { 2, 1, 1, 1 } }, // vpmovdb
2319 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdb
2320 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdb
2321 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdb
2322 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdw
2323 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdw
2324 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, { 2, 1, 1, 1 } }, // vpmovqb
2325 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, { 1, 1, 1, 1 } }, // vpshufb
2326 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqb
2327 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqb
2328 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqb
2329 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqb
2330 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqw
2331 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqw
2332 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqw
2333 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, { 1, 1, 1, 1 } }, // vpmovqd
2334 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, { 1, 1, 1, 1 } }, // zmm vpmovqd
2335 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, { 5, 1, 1, 1 } },// 2*vpmovqd+concat+vpmovdb
2337 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 3, 1, 1, 1 } }, // extend to v16i32
2338 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, { 8, 1, 1, 1 } },
2339 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, { 8, 1, 1, 1 } },
2343 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 3, 1, 1, 1 } },
2344 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 4, 1, 1, 1 } },
2345 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 3, 1, 1, 1 } },
2346 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 4, 1, 1, 1 } },
2347 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 3, 1, 1, 1 } },
2348 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 4, 1, 1, 1 } },
2349 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, { 3, 1, 1, 1 } },
2350 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, { 4, 1, 1, 1 } },
2354 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 3, 1, 1, 1 } },
2355 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 4, 1, 1, 1 } },
2356 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 3, 1, 1, 1 } },
2357 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 4, 1, 1, 1 } },
2358 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, { 3, 1, 1, 1 } },
2359 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, { 4, 1, 1, 1 } },
2360 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 3, 1, 1, 1 } },
2361 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 4, 1, 1, 1 } },
2363 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, { 1, 1, 1, 1 } }, // zmm vpternlogd
2364 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, { 2, 1, 1, 1 } }, // zmm vpternlogd+psrld
2365 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, { 1, 1, 1, 1 } }, // zmm vpternlogd
2366 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, { 2, 1, 1, 1 } }, // zmm vpternlogd+psrld
2367 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 1, 1, 1, 1 } }, // zmm vpternlogd
2368 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 2, 1, 1, 1 } }, // zmm vpternlogd+psrld
2369 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, { 1, 1, 1, 1 } }, // zmm vpternlogq
2370 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, { 2, 1, 1, 1 } }, // zmm vpternlogq+psrlq
2371 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 1, 1, 1, 1 } }, // zmm vpternlogq
2372 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 2, 1, 1, 1 } }, // zmm vpternlogq+psrlq
2374 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, { 1, 1, 1, 1 } }, // vpternlogd
2375 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2376 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, { 1, 1, 1, 1 } }, // vpternlogq
2377 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, { 2, 1, 1, 1 } }, // vpternlogq+psrlq
2379 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, { 1, 1, 1, 1 } },
2380 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, { 1, 1, 1, 1 } },
2381 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, { 1, 1, 1, 1 } },
2382 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, { 1, 1, 1, 1 } },
2383 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, { 1, 1, 1, 1 } },
2384 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, { 1, 1, 1, 1 } },
2385 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, { 1, 1, 1, 1 } },
2386 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, { 1, 1, 1, 1 } },
2387 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, { 1, 1, 1, 1 } },
2388 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, { 1, 1, 1, 1 } },
2390 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, { 3, 1, 1, 1 } }, // FIXME: May not be right
2391 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, { 3, 1, 1, 1 } }, // FIXME: May not be right
2393 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, { 4, 1, 1, 1 } },
2394 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, { 3, 1, 1, 1 } },
2395 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, { 2, 1, 1, 1 } },
2396 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, { 1, 1, 1, 1 } },
2397 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, { 2, 1, 1, 1 } },
2398 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, { 1, 1, 1, 1 } },
2399 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, { 1, 1, 1, 1 } },
2400 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, { 1, 1, 1, 1 } },
2402 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, { 4, 1, 1, 1 } },
2403 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, { 3, 1, 1, 1 } },
2404 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, { 2, 1, 1, 1 } },
2405 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, { 1, 1, 1, 1 } },
2406 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, { 2, 1, 1, 1 } },
2407 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, { 1, 1, 1, 1 } },
2408 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, { 1, 1, 1, 1 } },
2409 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, { 1, 1, 1, 1 } },
2410 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, {26, 1, 1, 1 } },
2411 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, { 5, 1, 1, 1 } },
2413 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, { 2, 1, 1, 1 } },
2414 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, { 7, 1, 1, 1 } },
2415 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64, {15, 1, 1, 1 } },
2416 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32, {11, 1, 1, 1 } },
2417 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64, {31, 1, 1, 1 } },
2418 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, { 3, 1, 1, 1 } },
2419 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, { 7, 1, 1, 1 } },
2420 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, { 5, 1, 1, 1 } },
2421 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64, {15, 1, 1, 1 } },
2422 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, { 1, 1, 1, 1 } },
2423 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, { 3, 1, 1, 1 } },
2425 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, { 1, 1, 1, 1 } },
2426 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, { 3, 1, 1, 1 } },
2427 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, { 3, 1, 1, 1 } },
2428 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, { 1, 1, 1, 1 } },
2429 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, { 3, 1, 1, 1 } },
2430 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, { 3, 1, 1, 1 } },
2435 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 1, 1, 1, 1 } },
2436 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, { 1, 1, 1, 1 } },
2437 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 1, 1, 1, 1 } },
2438 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, { 1, 1, 1, 1 } },
2439 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 1, 1, 1, 1 } },
2440 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, { 1, 1, 1, 1 } },
2441 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 1, 1, 1, 1 } },
2442 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, { 1, 1, 1, 1 } },
2443 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 1, 1, 1, 1 } },
2444 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, { 1, 1, 1, 1 } },
2445 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, { 1, 1, 1, 1 } },
2446 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, { 1, 1, 1, 1 } },
2447 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 1, 1, 1, 1 } },
2448 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, { 1, 1, 1, 1 } },
2449 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, { 1, 1, 1, 1 } },
2450 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, { 1, 1, 1, 1 } },
2451 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, { 1, 1, 1, 1 } },
2454 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 2, 1, 1, 1 } },
2455 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, { 2, 1, 1, 1 } },
2456 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 2, 1, 1, 1 } },
2457 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, { 2, 1, 1, 1 } },
2458 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 2, 1, 1, 1 } },
2459 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, { 2, 1, 1, 1 } },
2460 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 2, 1, 1, 1 } },
2461 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, { 2, 1, 1, 1 } },
2462 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 2, 1, 1, 1 } },
2463 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, { 2, 1, 1, 1 } },
2464 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, { 2, 1, 1, 1 } },
2465 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, { 2, 1, 1, 1 } },
2466 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 2, 1, 1, 1 } },
2467 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, { 2, 1, 1, 1 } },
2468 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, { 2, 1, 1, 1 } },
2469 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, { 2, 1, 1, 1 } },
2470 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, { 2, 1, 1, 1 } },
2472 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 2, 1, 1, 1 } },
2473 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, { 2, 1, 1, 1 } },
2474 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 2, 1, 1, 1 } },
2475 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, { 2, 1, 1, 1 } },
2476 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 2, 1, 1, 1 } },
2477 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, { 2, 1, 1, 1 } },
2478 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 2, 1, 1, 1 } },
2479 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, { 2, 1, 1, 1 } },
2480 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 2, 1, 1, 1 } },
2481 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, { 2, 1, 1, 1 } },
2482 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, { 2, 1, 1, 1 } },
2483 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, { 2, 1, 1, 1 } },
2484 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 2, 1, 1, 1 } },
2485 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, { 2, 1, 1, 1 } },
2486 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, { 2, 1, 1, 1 } },
2487 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, { 2, 1, 1, 1 } },
2488 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, { 2, 1, 1, 1 } },
2490 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 2, 1, 1, 1 } },
2495 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, { 1, 1, 1, 1 } },
2496 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, { 1, 1, 1, 1 } },
2497 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, { 1, 1, 1, 1 } },
2498 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, { 1, 1, 1, 1 } },
2499 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 1, 1, 1, 1 } },
2500 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, { 1, 1, 1, 1 } },
2501 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, { 1, 1, 1, 1 } },
2502 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 1, 1, 1, 1 } },
2505 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, { 2, 1, 1, 1 } },
2506 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, { 2, 1, 1, 1 } },
2507 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, { 2, 1, 1, 1 } },
2508 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, { 2, 1, 1, 1 } },
2509 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 2, 1, 1, 1 } },
2510 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, { 2, 1, 1, 1 } },
2511 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, { 2, 1, 1, 1 } },
2512 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 2, 1, 1, 1 } },
2514 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, { 2, 1, 1, 1 } },
2515 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, { 2, 1, 1, 1 } },
2516 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, { 2, 1, 1, 1 } },
2517 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, { 2, 1, 1, 1 } },
2518 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, { 2, 1, 1, 1 } },
2519 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 2, 1, 1, 1 } },
2520 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, { 2, 1, 1, 1 } },
2521 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } },
2523 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, { 1, 1, 1, 1 } },
2524 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, { 1, 1, 1, 1 } },
2525 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, { 1, 1, 1, 1 } },
2526 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, { 1, 1, 1, 1 } },
2528 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, { 1, 1, 1, 1 } },
2529 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, { 1, 1, 1, 1 } },
2530 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, { 1, 1, 1, 1 } },
2531 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, { 1, 1, 1, 1 } },
2533 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, { 1, 1, 1, 1 } },
2534 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, { 1, 1, 1, 1 } },
2535 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, { 1, 1, 1, 1 } },
2536 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, { 1, 1, 1, 1 } },
2538 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, { 1, 1, 1, 1 } },
2539 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, { 1, 1, 1, 1 } },
2540 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, { 1, 1, 1, 1 } },
2541 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, { 1, 1, 1, 1 } },
2545 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2546 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2547 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2548 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, { 8, 1, 1, 1 } }, // split+2*v8i8
2549 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2550 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2551 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2552 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 8, 1, 1, 1 } }, // split+2*v8i16
2553 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2554 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2555 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2556 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2557 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, { 2, 1, 1, 1 } }, // vpsllq+vptestmq
2558 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 2, 1, 1, 1 } }, // vpsllq+vptestmq
2559 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, { 1, 1, 1, 1 } }, // vpmovqd
2560 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, { 2, 1, 1, 1 } }, // vpmovqb
2561 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, { 2, 1, 1, 1 } }, // vpmovqw
2562 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, { 2, 1, 1, 1 } }, // vpmovwb
2566 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 5, 1, 1, 1 } },
2567 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 6, 1, 1, 1 } },
2568 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 5, 1, 1, 1 } },
2569 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 6, 1, 1, 1 } },
2570 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 5, 1, 1, 1 } },
2571 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 6, 1, 1, 1 } },
2572 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, {10, 1, 1, 1 } },
2573 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, {12, 1, 1, 1 } },
2577 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 4, 1, 1, 1 } },
2578 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 5, 1, 1, 1 } },
2579 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 4, 1, 1, 1 } },
2580 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 5, 1, 1, 1 } },
2581 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, { 4, 1, 1, 1 } },
2582 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, { 5, 1, 1, 1 } },
2583 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, {10, 1, 1, 1 } },
2584 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, {12, 1, 1, 1 } },
2586 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, { 1, 1, 1, 1 } }, // vpternlogd
2587 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2588 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, { 1, 1, 1, 1 } }, // vpternlogd
2589 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2590 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 1, 1, 1, 1 } }, // vpternlogd
2591 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2592 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, { 1, 1, 1, 1 } }, // vpternlogd
2593 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2595 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, { 1, 1, 1, 1 } }, // vpternlogq
2596 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, { 2, 1, 1, 1 } }, // vpternlogq+psrlq
2597 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 1, 1, 1, 1 } }, // vpternlogq
2598 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 2, 1, 1, 1 } }, // vpternlogq+psrlq
2600 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, { 1, 1, 1, 1 } },
2601 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, { 1, 1, 1, 1 } },
2602 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, { 1, 1, 1, 1 } },
2603 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, { 1, 1, 1, 1 } },
2604 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, { 1, 1, 1, 1 } },
2605 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, { 1, 1, 1, 1 } },
2606 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, { 1, 1, 1, 1 } },
2607 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, { 1, 1, 1, 1 } },
2608 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, { 1, 1, 1, 1 } },
2609 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, { 1, 1, 1, 1 } },
2610 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, { 1, 1, 1, 1 } },
2611 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, { 1, 1, 1, 1 } },
2613 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, { 1, 1, 1, 1 } },
2614 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, { 1, 1, 1, 1 } },
2615 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, { 1, 1, 1, 1 } },
2616 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, { 1, 1, 1, 1 } },
2618 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, { 1, 1, 1, 1 } },
2619 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, { 1, 1, 1, 1 } },
2620 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, { 1, 1, 1, 1 } },
2621 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, { 1, 1, 1, 1 } },
2622 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, { 1, 1, 1, 1 } },
2623 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, { 1, 1, 1, 1 } },
2624 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 1, 1, 1, 1 } },
2625 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 1, 1, 1, 1 } },
2626 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, { 1, 1, 1, 1 } },
2627 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, { 1, 1, 1, 1 } },
2628 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, { 5, 1, 1, 1 } },
2629 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, { 5, 1, 1, 1 } },
2630 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, { 5, 1, 1, 1 } },
2632 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, { 2, 1, 1, 1 } },
2633 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, { 2, 1, 1, 1 } },
2634 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, { 5, 1, 1, 1 } },
2636 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, { 1, 1, 1, 1 } },
2637 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, { 1, 1, 1, 1 } },
2638 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 1, 1, 1, 1 } },
2639 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 1, 1, 1, 1 } },
2640 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, { 1, 1, 1, 1 } },
2641 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, { 1, 1, 1, 1 } },
2642 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, { 1, 1, 1, 1 } },
2646 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 3, 1, 1, 1 } },
2647 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 3, 1, 1, 1 } },
2648 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 3, 1, 1, 1 } },
2649 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 3, 1, 1, 1 } },
2650 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 1, 1, 1, 1 } },
2651 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 1, 1, 1, 1 } },
2653 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, { 2, 1, 1, 1 } },
2654 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, { 2, 1, 1, 1 } },
2655 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, { 2, 1, 1, 1 } },
2656 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, { 2, 1, 1, 1 } },
2657 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, { 2, 1, 1, 1 } },
2658 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, { 2, 1, 1, 1 } },
2659 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, { 2, 1, 1, 1 } },
2660 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, { 2, 1, 1, 1 } },
2661 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, { 2, 1, 1, 1 } },
2662 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, { 2, 1, 1, 1 } },
2663 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, { 3, 1, 1, 1 } },
2664 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, { 3, 1, 1, 1 } },
2665 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, { 2, 1, 1, 1 } },
2666 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, { 2, 1, 1, 1 } },
2668 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } },
2670 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, { 4, 1, 1, 1 } },
2671 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, { 4, 1, 1, 1 } },
2672 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, { 1, 1, 1, 1 } },
2673 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, { 1, 1, 1, 1 } },
2674 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, { 1, 1, 1, 1 } },
2675 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, { 4, 1, 1, 1 } },
2676 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, { 4, 1, 1, 1 } },
2677 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, { 1, 1, 1, 1 } },
2678 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, { 1, 1, 1, 1 } },
2679 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, { 5, 1, 1, 1 } },
2680 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, { 1, 1, 1, 1 } },
2681 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, { 2, 1, 1, 1 } },
2683 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, { 3, 1, 1, 1 } },
2684 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, { 3, 1, 1, 1 } },
2686 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, { 1, 1, 1, 1 } },
2687 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, { 1, 1, 1, 1 } },
2688 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, { 1, 1, 1, 1 } },
2689 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, { 3, 1, 1, 1 } },
2691 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, { 3, 1, 1, 1 } },
2692 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, { 3, 1, 1, 1 } },
2693 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, { 1, 1, 1, 1 } },
2694 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 3, 1, 1, 1 } },
2695 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 4, 1, 1, 1 } },
2696 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, { 4, 1, 1, 1 } },
2697 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, { 3, 1, 1, 1 } },
2698 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, { 4, 1, 1, 1 } },
2700 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, { 2, 1, 1, 1 } },
2701 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, { 2, 1, 1, 1 } },
2702 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, { 2, 1, 1, 1 } },
2703 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, { 2, 1, 1, 1 } },
2704 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, { 1, 1, 1, 1 } },
2705 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, { 1, 1, 1, 1 } },
2706 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, { 3, 1, 1, 1 } },
2708 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, { 2, 1, 1, 1 } },
2709 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, { 2, 1, 1, 1 } },
2710 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, { 2, 1, 1, 1 } },
2711 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, { 2, 1, 1, 1 } },
2712 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 2, 1, 1, 1 } },
2713 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, { 1, 1, 1, 1 } },
2714 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 2, 1, 1, 1 } },
2715 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, { 2, 1, 1, 1 } },
2716 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, { 2, 1, 1, 1 } },
2717 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, { 4, 1, 1, 1 } },
2721 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 4, 1, 1, 1 } },
2722 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 4, 1, 1, 1 } },
2723 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 4, 1, 1, 1 } },
2724 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 4, 1, 1, 1 } },
2725 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 4, 1, 1, 1 } },
2726 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 4, 1, 1, 1 } },
2728 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, { 3, 1, 1, 1 } },
2729 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, { 3, 1, 1, 1 } },
2730 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, { 3, 1, 1, 1 } },
2731 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, { 3, 1, 1, 1 } },
2732 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, { 3, 1, 1, 1 } },
2733 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, { 3, 1, 1, 1 } },
2734 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, { 3, 1, 1, 1 } },
2735 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, { 3, 1, 1, 1 } },
2736 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, { 3, 1, 1, 1 } },
2737 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, { 3, 1, 1, 1 } },
2738 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, { 3, 1, 1, 1 } },
2739 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, { 3, 1, 1, 1 } },
2741 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 4, 1, 1, 1 } },
2742 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 5, 1, 1, 1 } },
2743 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 4, 1, 1, 1 } },
2744 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, { 9, 1, 1, 1 } },
2745 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, {11, 1, 1, 1 } },
2747 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, { 6, 1, 1, 1 } },
2748 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, { 6, 1, 1, 1 } },
2749 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 2, 1, 1, 1 } }, // and+extract+packuswb
2750 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, { 5, 1, 1, 1 } },
2751 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, { 5, 1, 1, 1 } },
2752 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, { 5, 1, 1, 1 } },
2753 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, { 3, 1, 1, 1 } }, // and+extract+2*packusdw
2754 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, { 2, 1, 1, 1 } },
2756 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, { 3, 1, 1, 1 } },
2757 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, { 3, 1, 1, 1 } },
2758 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, { 8, 1, 1, 1 } },
2759 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, { 4, 1, 1, 1 } },
2760 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, { 2, 1, 1, 1 } },
2761 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, { 4, 1, 1, 1 } },
2762 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, { 2, 1, 1, 1 } },
2763 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, { 2, 1, 1, 1 } },
2764 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, { 2, 1, 1, 1 } },
2765 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, { 4, 1, 1, 1 } },
2766 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, { 5, 1, 1, 1 } },
2767 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, { 8, 1, 1, 1 } },
2769 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, { 7, 1, 1, 1 } },
2770 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, { 7, 1, 1, 1 } },
2771 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, { 6, 1, 1, 1 } },
2772 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, { 4, 1, 1, 1 } },
2773 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, { 2, 1, 1, 1 } },
2774 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, { 4, 1, 1, 1 } },
2775 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, { 2, 1, 1, 1 } },
2776 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 4, 1, 1, 1 } },
2777 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, { 4, 1, 1, 1 } },
2778 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 5, 1, 1, 1 } },
2779 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, { 6, 1, 1, 1 } },
2780 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, { 8, 1, 1, 1 } },
2781 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, {10, 1, 1, 1 } },
2782 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, {10, 1, 1, 1 } },
2783 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, {18, 1, 1, 1 } },
2784 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, { 5, 1, 1, 1 } },
2785 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, {10, 1, 1, 1 } },
2787 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, { 2, 1, 1, 1 } },
2788 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, { 2, 1, 1, 1 } },
2789 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, { 2, 1, 1, 1 } },
2790 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, { 2, 1, 1, 1 } },
2791 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, { 2, 1, 1, 1 } },
2792 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, { 2, 1, 1, 1 } },
2793 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, { 2, 1, 1, 1 } },
2794 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, { 2, 1, 1, 1 } },
2795 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, { 2, 1, 1, 1 } },
2796 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, { 2, 1, 1, 1 } },
2797 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, { 5, 1, 1, 1 } },
2799 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, { 2, 1, 1, 1 } },
2800 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, { 2, 1, 1, 1 } },
2801 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, { 2, 1, 1, 1 } },
2802 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, { 2, 1, 1, 1 } },
2803 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, { 2, 1, 1, 1 } },
2804 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, { 2, 1, 1, 1 } },
2805 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, { 2, 1, 1, 1 } },
2806 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, { 2, 1, 1, 1 } },
2807 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 3, 1, 1, 1 } },
2808 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 4, 1, 1, 1 } },
2809 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, { 6, 1, 1, 1 } },
2810 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, { 7, 1, 1, 1 } },
2811 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, { 7, 1, 1, 1 } },
2813 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, { 1, 1, 1, 1 } },
2814 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, { 1, 1, 1, 1 } },
2818 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, { 1, 1, 1, 1 } },
2819 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, { 1, 1, 1, 1 } },
2820 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, { 1, 1, 1, 1 } },
2821 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, { 1, 1, 1, 1 } },
2822 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, { 1, 1, 1, 1 } },
2823 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, { 1, 1, 1, 1 } },
2824 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, { 1, 1, 1, 1 } },
2825 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, { 1, 1, 1, 1 } },
2826 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, { 1, 1, 1, 1 } },
2827 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, { 1, 1, 1, 1 } },
2828 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, { 1, 1, 1, 1 } },
2829 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, { 1, 1, 1, 1 } },
2832 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 1, 1, 1, 1 } }, // PMOVXZBQ
2833 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 1, 1, 1, 1 } }, // PMOVXZWQ
2834 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 1, 1, 1, 1 } }, // PMOVXZBD
2836 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, { 2, 1, 1, 1 } },
2837 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, { 2, 1, 1, 1 } },
2838 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, { 2, 1, 1, 1 } },
2840 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, { 1, 1, 1, 1 } },
2841 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, { 1, 1, 1, 1 } },
2842 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, { 1, 1, 1, 1 } },
2843 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, { 1, 1, 1, 1 } },
2844 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, { 1, 1, 1, 1 } },
2845 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, { 1, 1, 1, 1 } },
2846 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, { 1, 1, 1, 1 } },
2847 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, { 1, 1, 1, 1 } },
2848 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, { 1, 1, 1, 1 } },
2849 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, { 1, 1, 1, 1 } },
2850 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, { 2, 1, 1, 1 } },
2852 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, { 1, 1, 1, 1 } },
2853 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, { 1, 1, 1, 1 } },
2854 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, { 4, 1, 1, 1 } },
2855 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, { 4, 1, 1, 1 } },
2856 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, { 1, 1, 1, 1 } },
2857 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, { 1, 1, 1, 1 } },
2858 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, { 1, 1, 1, 1 } },
2859 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, { 1, 1, 1, 1 } },
2860 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 3, 1, 1, 1 } },
2861 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 3, 1, 1, 1 } },
2862 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, { 2, 1, 1, 1 } },
2863 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, {12, 1, 1, 1 } },
2864 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, {22, 1, 1, 1 } },
2865 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, { 4, 1, 1, 1 } },
2867 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, { 1, 1, 1, 1 } },
2868 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, { 1, 1, 1, 1 } },
2869 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, { 1, 1, 1, 1 } },
2870 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, { 1, 1, 1, 1 } },
2871 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, { 2, 1, 1, 1 } },
2872 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, { 2, 1, 1, 1 } },
2873 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, { 1, 1, 1, 1 } },
2874 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, { 1, 1, 1, 1 } },
2875 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, { 1, 1, 1, 1 } },
2876 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, { 1, 1, 1, 1 } },
2878 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, { 1, 1, 1, 1 } },
2879 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, { 4, 1, 1, 1 } },
2880 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, { 1, 1, 1, 1 } },
2881 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, { 4, 1, 1, 1 } },
2882 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, { 2, 1, 1, 1 } },
2883 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, { 2, 1, 1, 1 } },
2884 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, { 1, 1, 1, 1 } },
2885 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, { 1, 1, 1, 1 } },
2886 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 4, 1, 1, 1 } },
2887 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 4, 1, 1, 1 } },
2894 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, { 3, 1, 1, 1 } },
2895 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, { 3, 1, 1, 1 } },
2896 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, { 3, 1, 1, 1 } },
2897 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, { 3, 1, 1, 1 } },
2898 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, { 3, 1, 1, 1 } },
2899 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, { 4, 1, 1, 1 } },
2900 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, { 3, 1, 1, 1 } },
2901 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, { 4, 1, 1, 1 } },
2902 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, { 3, 1, 1, 1 } },
2903 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, { 4, 1, 1, 1 } },
2904 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, { 8, 1, 1, 1 } },
2905 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, { 8, 1, 1, 1 } },
2907 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, { 3, 1, 1, 1 } },
2908 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, { 3, 1, 1, 1 } },
2909 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, { 8, 1, 1, 1 } },
2910 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, { 9, 1, 1, 1 } },
2911 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, { 4, 1, 1, 1 } },
2912 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, { 4, 1, 1, 1 } },
2913 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, { 4, 1, 1, 1 } },
2914 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, { 4, 1, 1, 1 } },
2915 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 7, 1, 1, 1 } },
2916 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, { 7, 1, 1, 1 } },
2917 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 5, 1, 1, 1 } },
2918 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, {15, 1, 1, 1 } },
2919 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, {18, 1, 1, 1 } },
2921 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, { 4, 1, 1, 1 } },
2922 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, { 4, 1, 1, 1 } },
2923 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, { 4, 1, 1, 1 } },
2924 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, { 4, 1, 1, 1 } },
2925 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, { 6, 1, 1, 1 } },
2926 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, { 6, 1, 1, 1 } },
2927 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, { 5, 1, 1, 1 } },
2928 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, { 5, 1, 1, 1 } },
2929 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, { 4, 1, 1, 1 } },
2930 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, { 4, 1, 1, 1 } },
2932 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, { 4, 1, 1, 1 } },
2933 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, { 4, 1, 1, 1 } },
2934 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, { 4, 1, 1, 1 } },
2935 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, {15, 1, 1, 1 } },
2936 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, { 6, 1, 1, 1 } },
2937 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, { 6, 1, 1, 1 } },
2938 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, { 5, 1, 1, 1 } },
2939 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, { 5, 1, 1, 1 } },
2940 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 8, 1, 1, 1 } },
2941 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 8, 1, 1, 1 } },
2943 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, { 4, 1, 1, 1 } },
2944 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, { 4, 1, 1, 1 } },
2945 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, { 2, 1, 1, 1 } },
2946 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, { 3, 1, 1, 1 } },
2947 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, { 1, 1, 1, 1 } },
2948 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, { 2, 1, 1, 1 } },
2949 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, { 2, 1, 1, 1 } },
2950 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, { 3, 1, 1, 1 } },
2951 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, { 1, 1, 1, 1 } },
2952 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, { 2, 1, 1, 1 } },
2953 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, { 1, 1, 1, 1 } },
2954 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, { 2, 1, 1, 1 } },
2957 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, { 1, 1, 1, 1 } }, // PSHUFD
2958 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 2, 1, 1, 1 } }, // PUNPCKLWD+DQ
2959 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 3, 1, 1, 1 } }, // PUNPCKLBW+WD+PSHUFD
2960 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 1, 1, 1, 1 } }, // PUNPCKLWD
2961 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 2, 1, 1, 1 } }, // PUNPCKLBW+WD
2962 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 1, 1, 1, 1 } }, // PUNPCKLBW
2964 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, { 2, 1, 1, 1 } }, // PAND+PACKUSWB
2965 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 3, 1, 1, 1 } },
2966 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, { 3, 1, 1, 1 } }, // PAND+2*PACKUSWB
2967 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, { 7, 1, 1, 1 } },
2968 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, { 1, 1, 1, 1 } },
2969 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, { 3, 1, 1, 1 } },
2970 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, { 5, 1, 1, 1 } },
2971 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, {10, 1, 1, 1 } },
2972 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, { 4, 1, 1, 1 } }, // PAND+3*PACKUSWB
2973 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, { 2, 1, 1, 1 } }, // PSHUFD+PSHUFLW
2974 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, { 1, 1, 1, 1 } }, // PSHUFD
2989 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
2995 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3001 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3008 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3014 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3019 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
3025 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
3032 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
3039 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
3046 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
3058 if (ISD == ISD::TRUNCATE && LTSrc.second == LTDest.second)
3064 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second))
3070 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second))
3076 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second))
3082 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD,
3088 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD,
3094 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
3100 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
3106 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
3112 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
3118 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
3125 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) &&
3129 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt;
3142 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) &&
3176 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3177 assert(ISD && "Invalid opcode");
3252 { ISD::SETCC, MVT::v2i64, { 2, 5, 1, 2 } },
3254 { ISD::SELECT, MVT::v2f64, { 4, 4, 1, 3 } }, // vblendvpd
3255 { ISD::SELECT, MVT::v4f32, { 4, 4, 1, 3 } }, // vblendvps
3256 { ISD::SELECT, MVT::v2i64, { 4, 4, 1, 3 } }, // pblendvb
3257 { ISD::SELECT, MVT::v8i32, { 4, 4, 1, 3 } }, // pblendvb
3258 { ISD::SELECT, MVT::v8i16, { 4, 4, 1, 3 } }, // pblendvb
3259 { ISD::SELECT, MVT::v16i8, { 4, 4, 1, 3 } }, // pblendvb
3263 { ISD::SETCC, MVT::v32i16, { 1, 1, 1, 1 } },
3264 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 1 } },
3265 { ISD::SETCC, MVT::v64i8, { 1, 1, 1, 1 } },
3266 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 1 } },
3268 { ISD::SELECT, MVT::v32i16, { 1, 1, 1, 1 } },
3269 { ISD::SELECT, MVT::v64i8, { 1, 1, 1, 1 } },
3273 { ISD::SETCC, MVT::v8f64, { 1, 4, 1, 1 } },
3274 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 1 } },
3275 { ISD::SETCC, MVT::v16f32, { 1, 4, 1, 1 } },
3276 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 1 } },
3278 { ISD::SETCC, MVT::v8i64, { 1, 1, 1, 1 } },
3279 { ISD::SETCC, MVT::v4i64, { 1, 1, 1, 1 } },
3280 { ISD::SETCC, MVT::v2i64, { 1, 1, 1, 1 } },
3281 { ISD::SETCC, MVT::v16i32, { 1, 1, 1, 1 } },
3282 { ISD::SETCC, MVT::v8i32, { 1, 1, 1, 1 } },
3283 { ISD::SETCC, MVT::v32i16, { 3, 7, 5, 5 } },
3284 { ISD::SETCC, MVT::v64i8, { 3, 7, 5, 5 } },
3286 { ISD::SELECT, MVT::v8i64, { 1, 1, 1, 1 } },
3287 { ISD::SELECT, MVT::v4i64, { 1, 1, 1, 1 } },
3288 { ISD::SELECT, MVT::v2i64, { 1, 1, 1, 1 } },
3289 { ISD::SELECT, MVT::v16i32, { 1, 1, 1, 1 } },
3290 { ISD::SELECT, MVT::v8i32, { 1, 1, 1, 1 } },
3291 { ISD::SELECT, MVT::v4i32, { 1, 1, 1, 1 } },
3292 { ISD::SELECT, MVT::v8f64, { 1, 1, 1, 1 } },
3293 { ISD::SELECT, MVT::v4f64, { 1, 1, 1, 1 } },
3294 { ISD::SELECT, MVT::v2f64, { 1, 1, 1, 1 } },
3295 { ISD::SELECT, MVT::f64, { 1, 1, 1, 1 } },
3296 { ISD::SELECT, MVT::v16f32, { 1, 1, 1, 1 } },
3297 { ISD::SELECT, MVT::v8f32 , { 1, 1, 1, 1 } },
3298 { ISD::SELECT, MVT::v4f32, { 1, 1, 1, 1 } },
3299 { ISD::SELECT, MVT::f32 , { 1, 1, 1, 1 } },
3301 { ISD::SELECT, MVT::v32i16, { 2, 2, 4, 4 } },
3302 { ISD::SELECT, MVT::v16i16, { 1, 1, 1, 1 } },
3303 { ISD::SELECT, MVT::v8i16, { 1, 1, 1, 1 } },
3304 { ISD::SELECT, MVT::v64i8, { 2, 2, 4, 4 } },
3305 { ISD::SELECT, MVT::v32i8, { 1, 1, 1, 1 } },
3306 { ISD::SELECT, MVT::v16i8, { 1, 1, 1, 1 } },
3310 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 2 } },
3311 { ISD::SETCC, MVT::v2f64, { 1, 4, 1, 1 } },
3312 { ISD::SETCC, MVT::f64, { 1, 4, 1, 1 } },
3313 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 2 } },
3314 { ISD::SETCC, MVT::v4f32, { 1, 4, 1, 1 } },
3315 { ISD::SETCC, MVT::f32, { 1, 4, 1, 1 } },
3317 { ISD::SETCC, MVT::v4i64, { 1, 1, 1, 2 } },
3318 { ISD::SETCC, MVT::v8i32, { 1, 1, 1, 2 } },
3319 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 2 } },
3320 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 2 } },
3322 { ISD::SELECT, MVT::v4f64, { 2, 2, 1, 2 } }, // vblendvpd
3323 { ISD::SELECT, MVT::v8f32, { 2, 2, 1, 2 } }, // vblendvps
3324 { ISD::SELECT, MVT::v4i64, { 2, 2, 1, 2 } }, // pblendvb
3325 { ISD::SELECT, MVT::v8i32, { 2, 2, 1, 2 } }, // pblendvb
3326 { ISD::SELECT, MVT::v16i16, { 2, 2, 1, 2 } }, // pblendvb
3327 { ISD::SELECT, MVT::v32i8, { 2, 2, 1, 2 } }, // pblendvb
3331 { ISD::SETCC, MVT::v4i64, { 4, 2, 5, 6 } },
3332 { ISD::SETCC, MVT::v2i64, { 1, 1, 1, 1 } },
3336 { ISD::SETCC, MVT::v4f64, { 2, 3, 1, 2 } },
3337 { ISD::SETCC, MVT::v2f64, { 1, 3, 1, 1 } },
3338 { ISD::SETCC, MVT::f64, { 1, 3, 1, 1 } },
3339 { ISD::SETCC, MVT::v8f32, { 2, 3, 1, 2 } },
3340 { ISD::SETCC, MVT::v4f32, { 1, 3, 1, 1 } },
3341 { ISD::SETCC, MVT::f32, { 1, 3, 1, 1 } },
3344 { ISD::SETCC, MVT::v4i64, { 4, 2, 5, 6 } },
3345 { ISD::SETCC, MVT::v8i32, { 4, 2, 5, 6 } },
3346 { ISD::SETCC, MVT::v16i16, { 4, 2, 5, 6 } },
3347 { ISD::SETCC, MVT::v32i8, { 4, 2, 5, 6 } },
3349 { ISD::SELECT, MVT::v4f64, { 3, 3, 1, 2 } }, // vblendvpd
3350 { ISD::SELECT, MVT::v8f32, { 3, 3, 1, 2 } }, // vblendvps
3351 { ISD::SELECT, MVT::v4i64, { 3, 3, 1, 2 } }, // vblendvpd
3352 { ISD::SELECT, MVT::v8i32, { 3, 3, 1, 2 } }, // vblendvps
3353 { ISD::SELECT, MVT::v16i16, { 3, 3, 3, 3 } }, // vandps + vandnps + vorps
3354 { ISD::SELECT, MVT::v32i8, { 3, 3, 3, 3 } }, // vandps + vandnps + vorps
3358 { ISD::SETCC, MVT::v2i64, { 1, 2, 1, 2 } },
3362 { ISD::SETCC, MVT::v2f64, { 1, 5, 1, 1 } },
3363 { ISD::SETCC, MVT::v4f32, { 1, 5, 1, 1 } },
3365 { ISD::SELECT, MVT::v2f64, { 2, 2, 1, 2 } }, // blendvpd
3366 { ISD::SELECT, MVT::f64, { 2, 2, 1, 2 } }, // blendvpd
3367 { ISD::SELECT, MVT::v4f32, { 2, 2, 1, 2 } }, // blendvps
3368 { ISD::SELECT, MVT::f32 , { 2, 2, 1, 2 } }, // blendvps
3369 { ISD::SELECT, MVT::v2i64, { 2, 2, 1, 2 } }, // pblendvb
3370 { ISD::SELECT, MVT::v4i32, { 2, 2, 1, 2 } }, // pblendvb
3371 { ISD::SELECT, MVT::v8i16, { 2, 2, 1, 2 } }, // pblendvb
3372 { ISD::SELECT, MVT::v16i8, { 2, 2, 1, 2 } }, // pblendvb
3376 { ISD::SETCC, MVT::v2f64, { 2, 5, 1, 1 } },
3377 { ISD::SETCC, MVT::f64, { 1, 5, 1, 1 } },
3379 { ISD::SETCC, MVT::v2i64, { 5, 4, 5, 5 } }, // pcmpeqd/pcmpgtd expansion
3380 { ISD::SETCC, MVT::v4i32, { 1, 1, 1, 1 } },
3381 { ISD::SETCC, MVT::v8i16, { 1, 1, 1, 1 } },
3382 { ISD::SETCC, MVT::v16i8, { 1, 1, 1, 1 } },
3384 { ISD::SELECT, MVT::v2f64, { 2, 2, 3, 3 } }, // andpd + andnpd + orpd
3385 { ISD::SELECT, MVT::f64, { 2, 2, 3, 3 } }, // andpd + andnpd + orpd
3386 { ISD::SELECT, MVT::v2i64, { 2, 2, 3, 3 } }, // pand + pandn + por
3387 { ISD::SELECT, MVT::v4i32, { 2, 2, 3, 3 } }, // pand + pandn + por
3388 { ISD::SELECT, MVT::v8i16, { 2, 2, 3, 3 } }, // pand + pandn + por
3389 { ISD::SELECT, MVT::v16i8, { 2, 2, 3, 3 } }, // pand + pandn + por
3393 { ISD::SETCC, MVT::v4f32, { 2, 5, 1, 1 } },
3394 { ISD::SETCC, MVT::f32, { 1, 5, 1, 1 } },
3396 { ISD::SELECT, MVT::v4f32, { 2, 2, 3, 3 } }, // andps + andnps + orps
3397 { ISD::SELECT, MVT::f32, { 2, 2, 3, 3 } }, // andps + andnps + orps
3401 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
3406 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
3411 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
3416 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
3421 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
3426 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
3431 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
3436 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
3441 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
3446 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
3473 { ISD::FSHL, MVT::v8i64, { 1, 1, 1, 1 } },
3474 { ISD::FSHL, MVT::v4i64, { 1, 1, 1, 1 } },
3475 { ISD::FSHL, MVT::v2i64, { 1, 1, 1, 1 } },
3476 { ISD::FSHL, MVT::v16i32, { 1, 1, 1, 1 } },
3477 { ISD::FSHL, MVT::v8i32, { 1, 1, 1, 1 } },
3478 { ISD::FSHL, MVT::v4i32, { 1, 1, 1, 1 } },
3479 { ISD::FSHL, MVT::v32i16, { 1, 1, 1, 1 } },
3480 { ISD::FSHL, MVT::v16i16, { 1, 1, 1, 1 } },
3481 { ISD::FSHL, MVT::v8i16, { 1, 1, 1, 1 } },
3482 { ISD::ROTL, MVT::v32i16, { 1, 1, 1, 1 } },
3483 { ISD::ROTL, MVT::v16i16, { 1, 1, 1, 1 } },
3484 { ISD::ROTL, MVT::v8i16, { 1, 1, 1, 1 } },
3485 { ISD::ROTR, MVT::v32i16, { 1, 1, 1, 1 } },
3486 { ISD::ROTR, MVT::v16i16, { 1, 1, 1, 1 } },
3487 { ISD::ROTR, MVT::v8i16, { 1, 1, 1, 1 } },
3493 { ISD::CTPOP, MVT::v32i16, { 1, 1, 1, 1 } },
3494 { ISD::CTPOP, MVT::v64i8, { 1, 1, 1, 1 } },
3495 { ISD::CTPOP, MVT::v16i16, { 1, 1, 1, 1 } },
3496 { ISD::CTPOP, MVT::v32i8, { 1, 1, 1, 1 } },
3497 { ISD::CTPOP, MVT::v8i16, { 1, 1, 1, 1 } },
3498 { ISD::CTPOP, MVT::v16i8, { 1, 1, 1, 1 } },
3501 { ISD::CTPOP, MVT::v8i64, { 1, 1, 1, 1 } },
3502 { ISD::CTPOP, MVT::v16i32, { 1, 1, 1, 1 } },
3503 { ISD::CTPOP, MVT::v4i64, { 1, 1, 1, 1 } },
3504 { ISD::CTPOP, MVT::v8i32, { 1, 1, 1, 1 } },
3505 { ISD::CTPOP, MVT::v2i64, { 1, 1, 1, 1 } },
3506 { ISD::CTPOP, MVT::v4i32, { 1, 1, 1, 1 } },
3509 { ISD::CTLZ, MVT::v8i64, { 1, 5, 1, 1 } },
3510 { ISD::CTLZ, MVT::v16i32, { 1, 5, 1, 1 } },
3511 { ISD::CTLZ, MVT::v32i16, { 18, 27, 23, 27 } },
3512 { ISD::CTLZ, MVT::v64i8, { 3, 16, 9, 11 } },
3513 { ISD::CTLZ, MVT::v4i64, { 1, 5, 1, 1 } },
3514 { ISD::CTLZ, MVT::v8i32, { 1, 5, 1, 1 } },
3515 { ISD::CTLZ, MVT::v16i16, { 8, 19, 11, 13 } },
3516 { ISD::CTLZ, MVT::v32i8, { 2, 11, 9, 10 } },
3517 { ISD::CTLZ, MVT::v2i64, { 1, 5, 1, 1 } },
3518 { ISD::CTLZ, MVT::v4i32, { 1, 5, 1, 1 } },
3519 { ISD::CTLZ, MVT::v8i16, { 3, 15, 4, 6 } },
3520 { ISD::CTLZ, MVT::v16i8, { 2, 10, 9, 10 } },
3522 { ISD::CTTZ, MVT::v8i64, { 2, 8, 6, 7 } },
3523 { ISD::CTTZ, MVT::v16i32, { 2, 8, 6, 7 } },
3524 { ISD::CTTZ, MVT::v4i64, { 1, 8, 6, 6 } },
3525 { ISD::CTTZ, MVT::v8i32, { 1, 8, 6, 6 } },
3526 { ISD::CTTZ, MVT::v2i64, { 1, 8, 6, 6 } },
3527 { ISD::CTTZ, MVT::v4i32, { 1, 8, 6, 6 } },
3530 { ISD::ABS, MVT::v32i16, { 1, 1, 1, 1 } },
3531 { ISD::ABS, MVT::v64i8, { 1, 1, 1, 1 } },
3532 { ISD::BITREVERSE, MVT::v2i64, { 3, 10, 10, 11 } },
3533 { ISD::BITREVERSE, MVT::v4i64, { 3, 11, 10, 11 } },
3534 { ISD::BITREVERSE, MVT::v8i64, { 3, 12, 10, 14 } },
3535 { ISD::BITREVERSE, MVT::v4i32, { 3, 10, 10, 11 } },
3536 { ISD::BITREVERSE, MVT::v8i32, { 3, 11, 10, 11 } },
3537 { ISD::BITREVERSE, MVT::v16i32, { 3, 12, 10, 14 } },
3538 { ISD::BITREVERSE, MVT::v8i16, { 3, 10, 10, 11 } },
3539 { ISD::BITREVERSE, MVT::v16i16, { 3, 11, 10, 11 } },
3540 { ISD::BITREVERSE, MVT::v32i16, { 3, 12, 10, 14 } },
3541 { ISD::BITREVERSE, MVT::v16i8, { 2, 5, 9, 9 } },
3542 { ISD::BITREVERSE, MVT::v32i8, { 2, 5, 9, 9 } },
3543 { ISD::BITREVERSE, MVT::v64i8, { 2, 5, 9, 12 } },
3544 { ISD::BSWAP, MVT::v2i64, { 1, 1, 1, 2 } },
3545 { ISD::BSWAP, MVT::v4i64, { 1, 1, 1, 2 } },
3546 { ISD::BSWAP, MVT::v8i64, { 1, 1, 1, 2 } },
3547 { ISD::BSWAP, MVT::v4i32, { 1, 1, 1, 2 } },
3548 { ISD::BSWAP, MVT::v8i32, { 1, 1, 1, 2 } },
3549 { ISD::BSWAP, MVT::v16i32, { 1, 1, 1, 2 } },
3550 { ISD::BSWAP, MVT::v8i16, { 1, 1, 1, 2 } },
3551 { ISD::BSWAP, MVT::v16i16, { 1, 1, 1, 2 } },
3552 { ISD::BSWAP, MVT::v32i16, { 1, 1, 1, 2 } },
3553 { ISD::CTLZ, MVT::v8i64, { 8, 22, 23, 23 } },
3554 { ISD::CTLZ, MVT::v16i32, { 8, 23, 25, 25 } },
3555 { ISD::CTLZ, MVT::v32i16, { 4, 15, 15, 16 } },
3556 { ISD::CTLZ, MVT::v64i8, { 3, 12, 10, 9 } },
3557 { ISD::CTPOP, MVT::v2i64, { 3, 7, 10, 10 } },
3558 { ISD::CTPOP, MVT::v4i64, { 3, 7, 10, 10 } },
3559 { ISD::CTPOP, MVT::v8i64, { 3, 8, 10, 12 } },
3560 { ISD::CTPOP, MVT::v4i32, { 7, 11, 14, 14 } },
3561 { ISD::CTPOP, MVT::v8i32, { 7, 11, 14, 14 } },
3562 { ISD::CTPOP, MVT::v16i32, { 7, 12, 14, 16 } },
3563 { ISD::CTPOP, MVT::v8i16, { 2, 7, 11, 11 } },
3564 { ISD::CTPOP, MVT::v16i16, { 2, 7, 11, 11 } },
3565 { ISD::CTPOP, MVT::v32i16, { 3, 7, 11, 13 } },
3566 { ISD::CTPOP, MVT::v16i8, { 2, 4, 8, 8 } },
3567 { ISD::CTPOP, MVT::v32i8, { 2, 4, 8, 8 } },
3568 { ISD::CTPOP, MVT::v64i8, { 2, 5, 8, 10 } },
3569 { ISD::CTTZ, MVT::v8i16, { 3, 9, 14, 14 } },
3570 { ISD::CTTZ, MVT::v16i16, { 3, 9, 14, 14 } },
3571 { ISD::CTTZ, MVT::v32i16, { 3, 10, 14, 16 } },
3572 { ISD::CTTZ, MVT::v16i8, { 2, 6, 11, 11 } },
3573 { ISD::CTTZ, MVT::v32i8, { 2, 6, 11, 11 } },
3574 { ISD::CTTZ, MVT::v64i8, { 3, 7, 11, 13 } },
3575 { ISD::ROTL, MVT::v32i16, { 2, 8, 6, 8 } },
3576 { ISD::ROTL, MVT::v16i16, { 2, 8, 6, 7 } },
3577 { ISD::ROTL, MVT::v8i16, { 2, 7, 6, 7 } },
3578 { ISD::ROTL, MVT::v64i8, { 5, 6, 11, 12 } },
3579 { ISD::ROTL, MVT::v32i8, { 5, 15, 7, 10 } },
3580 { ISD::ROTL, MVT::v16i8, { 5, 15, 7, 10 } },
3581 { ISD::ROTR, MVT::v32i16, { 2, 8, 6, 8 } },
3582 { ISD::ROTR, MVT::v16i16, { 2, 8, 6, 7 } },
3583 { ISD::ROTR, MVT::v8i16, { 2, 7, 6, 7 } },
3584 { ISD::ROTR, MVT::v64i8, { 5, 6, 12, 14 } },
3585 { ISD::ROTR, MVT::v32i8, { 5, 14, 6, 9 } },
3586 { ISD::ROTR, MVT::v16i8, { 5, 14, 6, 9 } },
3593 { ISD::SADDSAT, MVT::v32i16, { 1 } },
3594 { ISD::SADDSAT, MVT::v64i8, { 1 } },
3595 { ISD::SMAX, MVT::v32i16, { 1, 1, 1, 1 } },
3596 { ISD::SMAX, MVT::v64i8, { 1, 1, 1, 1 } },
3597 { ISD::SMIN, MVT::v32i16, { 1, 1, 1, 1 } },
3598 { ISD::SMIN, MVT::v64i8, { 1, 1, 1, 1 } },
3599 { ISD::SSUBSAT, MVT::v32i16, { 1 } },
3600 { ISD::SSUBSAT, MVT::v64i8, { 1 } },
3601 { ISD::UADDSAT, MVT::v32i16, { 1 } },
3602 { ISD::UADDSAT, MVT::v64i8, { 1 } },
3603 { ISD::UMAX, MVT::v32i16, { 1, 1, 1, 1 } },
3604 { ISD::UMAX, MVT::v64i8, { 1, 1, 1, 1 } },
3605 { ISD::UMIN, MVT::v32i16, { 1, 1, 1, 1 } },
3606 { ISD::UMIN, MVT::v64i8, { 1, 1, 1, 1 } },
3607 { ISD::USUBSAT, MVT::v32i16, { 1 } },
3608 { ISD::USUBSAT, MVT::v64i8, { 1 } },
3611 { ISD::ABS, MVT::v8i64, { 1, 1, 1, 1 } },
3612 { ISD::ABS, MVT::v4i64, { 1, 1, 1, 1 } },
3613 { ISD::ABS, MVT::v2i64, { 1, 1, 1, 1 } },
3614 { ISD::ABS, MVT::v16i32, { 1, 1, 1, 1 } },
3615 { ISD::ABS, MVT::v8i32, { 1, 1, 1, 1 } },
3616 { ISD::ABS, MVT::v32i16, { 2, 7, 4, 4 } },
3617 { ISD::ABS, MVT::v16i16, { 1, 1, 1, 1 } },
3618 { ISD::ABS, MVT::v64i8, { 2, 7, 4, 4 } },
3619 { ISD::ABS, MVT::v32i8, { 1, 1, 1, 1 } },
3620 { ISD::BITREVERSE, MVT::v8i64, { 9, 13, 20, 20 } },
3621 { ISD::BITREVERSE, MVT::v16i32, { 9, 13, 20, 20 } },
3622 { ISD::BITREVERSE, MVT::v32i16, { 9, 13, 20, 20 } },
3623 { ISD::BITREVERSE, MVT::v64i8, { 6, 11, 17, 17 } },
3624 { ISD::BSWAP, MVT::v8i64, { 4, 7, 5, 5 } },
3625 { ISD::BSWAP, MVT::v16i32, { 4, 7, 5, 5 } },
3626 { ISD::BSWAP, MVT::v32i16, { 4, 7, 5, 5 } },
3627 { ISD::CTLZ, MVT::v8i64, { 10, 28, 32, 32 } },
3628 { ISD::CTLZ, MVT::v16i32, { 12, 30, 38, 38 } },
3629 { ISD::CTLZ, MVT::v32i16, { 8, 15, 29, 29 } },
3630 { ISD::CTLZ, MVT::v64i8, { 6, 11, 19, 19 } },
3631 { ISD::CTPOP, MVT::v8i64, { 16, 16, 19, 19 } },
3632 { ISD::CTPOP, MVT::v16i32, { 24, 19, 27, 27 } },
3633 { ISD::CTPOP, MVT::v32i16, { 18, 15, 22, 22 } },
3634 { ISD::CTPOP, MVT::v64i8, { 12, 11, 16, 16 } },
3635 { ISD::CTTZ, MVT::v8i64, { 2, 8, 6, 7 } },
3636 { ISD::CTTZ, MVT::v16i32, { 2, 8, 6, 7 } },
3637 { ISD::CTTZ, MVT::v32i16, { 7, 17, 27, 27 } },
3638 { ISD::CTTZ, MVT::v64i8, { 6, 13, 21, 21 } },
3639 { ISD::ROTL, MVT::v8i64, { 1, 1, 1, 1 } },
3640 { ISD::ROTL, MVT::v4i64, { 1, 1, 1, 1 } },
3641 { ISD::ROTL, MVT::v2i64, { 1, 1, 1, 1 } },
3642 { ISD::ROTL, MVT::v16i32, { 1, 1, 1, 1 } },
3643 { ISD::ROTL, MVT::v8i32, { 1, 1, 1, 1 } },
3644 { ISD::ROTL, MVT::v4i32, { 1, 1, 1, 1 } },
3645 { ISD::ROTR, MVT::v8i64, { 1, 1, 1, 1 } },
3646 { ISD::ROTR, MVT::v4i64, { 1, 1, 1, 1 } },
3647 { ISD::ROTR, MVT::v2i64, { 1, 1, 1, 1 } },
3648 { ISD::ROTR, MVT::v16i32, { 1, 1, 1, 1 } },
3649 { ISD::ROTR, MVT::v8i32, { 1, 1, 1, 1 } },
3650 { ISD::ROTR, MVT::v4i32, { 1, 1, 1, 1 } },
3657 { ISD::SMAX, MVT::v8i64, { 1, 3, 1, 1 } },
3658 { ISD::SMAX, MVT::v16i32, { 1, 1, 1, 1 } },
3659 { ISD::SMAX, MVT::v32i16, { 3, 7, 5, 5 } },
3660 { ISD::SMAX, MVT::v64i8, { 3, 7, 5, 5 } },
3661 { ISD::SMAX, MVT::v4i64, { 1, 3, 1, 1 } },
3662 { ISD::SMAX, MVT::v2i64, { 1, 3, 1, 1 } },
3663 { ISD::SMIN, MVT::v8i64, { 1, 3, 1, 1 } },
3664 { ISD::SMIN, MVT::v16i32, { 1, 1, 1, 1 } },
3665 { ISD::SMIN, MVT::v32i16, { 3, 7, 5, 5 } },
3666 { ISD::SMIN, MVT::v64i8, { 3, 7, 5, 5 } },
3667 { ISD::SMIN, MVT::v4i64, { 1, 3, 1, 1 } },
3668 { ISD::SMIN, MVT::v2i64, { 1, 3, 1, 1 } },
3669 { ISD::UMAX, MVT::v8i64, { 1, 3, 1, 1 } },
3670 { ISD::UMAX, MVT::v16i32, { 1, 1, 1, 1 } },
3671 { ISD::UMAX, MVT::v32i16, { 3, 7, 5, 5 } },
3672 { ISD::UMAX, MVT::v64i8, { 3, 7, 5, 5 } },
3673 { ISD::UMAX, MVT::v4i64, { 1, 3, 1, 1 } },
3674 { ISD::UMAX, MVT::v2i64, { 1, 3, 1, 1 } },
3675 { ISD::UMIN, MVT::v8i64, { 1, 3, 1, 1 } },
3676 { ISD::UMIN, MVT::v16i32, { 1, 1, 1, 1 } },
3677 { ISD::UMIN, MVT::v32i16, { 3, 7, 5, 5 } },
3678 { ISD::UMIN, MVT::v64i8, { 3, 7, 5, 5 } },
3679 { ISD::UMIN, MVT::v4i64, { 1, 3, 1, 1 } },
3680 { ISD::UMIN, MVT::v2i64, { 1, 3, 1, 1 } },
3681 { ISD::USUBSAT, MVT::v16i32, { 2 } }, // pmaxud + psubd
3682 { ISD::USUBSAT, MVT::v2i64, { 2 } }, // pmaxuq + psubq
3683 { ISD::USUBSAT, MVT::v4i64, { 2 } }, // pmaxuq + psubq
3684 { ISD::USUBSAT, MVT::v8i64, { 2 } }, // pmaxuq + psubq
3685 { ISD::UADDSAT, MVT::v16i32, { 3 } }, // not + pminud + paddd
3686 { ISD::UADDSAT, MVT::v2i64, { 3 } }, // not + pminuq + paddq
3687 { ISD::UADDSAT, MVT::v4i64, { 3 } }, // not + pminuq + paddq
3688 { ISD::UADDSAT, MVT::v8i64, { 3 } }, // not + pminuq + paddq
3689 { ISD::SADDSAT, MVT::v32i16, { 2 } },
3690 { ISD::SADDSAT, MVT::v64i8, { 2 } },
3691 { ISD::SSUBSAT, MVT::v32i16, { 2 } },
3692 { ISD::SSUBSAT, MVT::v64i8, { 2 } },
3693 { ISD::UADDSAT, MVT::v32i16, { 2 } },
3694 { ISD::UADDSAT, MVT::v64i8, { 2 } },
3695 { ISD::USUBSAT, MVT::v32i16, { 2 } },
3696 { ISD::USUBSAT, MVT::v64i8, { 2 } },
3697 { ISD::FMAXNUM, MVT::f32, { 2, 2, 3, 3 } },
3698 { ISD::FMAXNUM, MVT::v4f32, { 1, 1, 3, 3 } },
3699 { ISD::FMAXNUM, MVT::v8f32, { 2, 2, 3, 3 } },
3700 { ISD::FMAXNUM, MVT::v16f32, { 4, 4, 3, 3 } },
3701 { ISD::FMAXNUM, MVT::f64, { 2, 2, 3, 3 } },
3702 { ISD::FMAXNUM, MVT::v2f64, { 1, 1, 3, 3 } },
3703 { ISD::FMAXNUM, MVT::v4f64, { 2, 2, 3, 3 } },
3704 { ISD::FMAXNUM, MVT::v8f64, { 3, 3, 3, 3 } },
3705 { ISD::FSQRT, MVT::f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3706 { ISD::FSQRT, MVT::v4f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3707 { ISD::FSQRT, MVT::v8f32, { 6, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3708 { ISD::FSQRT, MVT::v16f32, { 12, 20, 1, 3 } }, // Skylake from http://www.agner.org/
3709 { ISD::FSQRT, MVT::f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3710 { ISD::FSQRT, MVT::v2f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3711 { ISD::FSQRT, MVT::v4f64, { 12, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3712 { ISD::FSQRT, MVT::v8f64, { 24, 32, 1, 3 } }, // Skylake from http://www.agner.org/
3715 { ISD::BITREVERSE, MVT::v4i64, { 3, 6, 5, 6 } },
3716 { ISD::BITREVERSE, MVT::v8i32, { 3, 6, 5, 6 } },
3717 { ISD::BITREVERSE, MVT::v16i16, { 3, 6, 5, 6 } },
3718 { ISD::BITREVERSE, MVT::v32i8, { 3, 6, 5, 6 } },
3719 { ISD::BITREVERSE, MVT::v2i64, { 2, 7, 1, 1 } },
3720 { ISD::BITREVERSE, MVT::v4i32, { 2, 7, 1, 1 } },
3721 { ISD::BITREVERSE, MVT::v8i16, { 2, 7, 1, 1 } },
3722 { ISD::BITREVERSE, MVT::v16i8, { 2, 7, 1, 1 } },
3723 { ISD::BITREVERSE, MVT::i64, { 2, 2, 3, 4 } },
3724 { ISD::BITREVERSE, MVT::i32, { 2, 2, 3, 4 } },
3725 { ISD::BITREVERSE, MVT::i16, { 2, 2, 3, 4 } },
3726 { ISD::BITREVERSE, MVT::i8, { 2, 2, 3, 4 } },
3728 { ISD::ROTL, MVT::v4i64, { 4, 7, 5, 6 } },
3729 { ISD::ROTL, MVT::v8i32, { 4, 7, 5, 6 } },
3730 { ISD::ROTL, MVT::v16i16, { 4, 7, 5, 6 } },
3731 { ISD::ROTL, MVT::v32i8, { 4, 7, 5, 6 } },
3732 { ISD::ROTL, MVT::v2i64, { 1, 3, 1, 1 } },
3733 { ISD::ROTL, MVT::v4i32, { 1, 3, 1, 1 } },
3734 { ISD::ROTL, MVT::v8i16, { 1, 3, 1, 1 } },
3735 { ISD::ROTL, MVT::v16i8, { 1, 3, 1, 1 } },
3736 { ISD::ROTR, MVT::v4i64, { 4, 7, 8, 9 } },
3737 { ISD::ROTR, MVT::v8i32, { 4, 7, 8, 9 } },
3738 { ISD::ROTR, MVT::v16i16, { 4, 7, 8, 9 } },
3739 { ISD::ROTR, MVT::v32i8, { 4, 7, 8, 9 } },
3740 { ISD::ROTR, MVT::v2i64, { 1, 3, 3, 3 } },
3741 { ISD::ROTR, MVT::v4i32, { 1, 3, 3, 3 } },
3742 { ISD::ROTR, MVT::v8i16, { 1, 3, 3, 3 } },
3743 { ISD::ROTR, MVT::v16i8, { 1, 3, 3, 3 } },
3754 { ISD::ABS, MVT::v2i64, { 2, 4, 3, 5 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
3755 { ISD::ABS, MVT::v4i64, { 2, 4, 3, 5 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
3756 { ISD::ABS, MVT::v4i32, { 1, 1, 1, 1 } },
3757 { ISD::ABS, MVT::v8i32, { 1, 1, 1, 2 } },
3758 { ISD::ABS, MVT::v8i16, { 1, 1, 1, 1 } },
3759 { ISD::ABS, MVT::v16i16, { 1, 1, 1, 2 } },
3760 { ISD::ABS, MVT::v16i8, { 1, 1, 1, 1 } },
3761 { ISD::ABS, MVT::v32i8, { 1, 1, 1, 2 } },
3762 { ISD::BITREVERSE, MVT::v2i64, { 3, 11, 10, 11 } },
3763 { ISD::BITREVERSE, MVT::v4i64, { 5, 11, 10, 17 } },
3764 { ISD::BITREVERSE, MVT::v4i32, { 3, 11, 10, 11 } },
3765 { ISD::BITREVERSE, MVT::v8i32, { 5, 11, 10, 17 } },
3766 { ISD::BITREVERSE, MVT::v8i16, { 3, 11, 10, 11 } },
3767 { ISD::BITREVERSE, MVT::v16i16, { 5, 11, 10, 17 } },
3768 { ISD::BITREVERSE, MVT::v16i8, { 3, 6, 9, 9 } },
3769 { ISD::BITREVERSE, MVT::v32i8, { 4, 5, 9, 15 } },
3770 { ISD::BSWAP, MVT::v2i64, { 1, 2, 1, 2 } },
3771 { ISD::BSWAP, MVT::v4i64, { 1, 3, 1, 2 } },
3772 { ISD::BSWAP, MVT::v4i32, { 1, 2, 1, 2 } },
3773 { ISD::BSWAP, MVT::v8i32, { 1, 3, 1, 2 } },
3774 { ISD::BSWAP, MVT::v8i16, { 1, 2, 1, 2 } },
3775 { ISD::BSWAP, MVT::v16i16, { 1, 3, 1, 2 } },
3776 { ISD::CTLZ, MVT::v2i64, { 7, 18, 24, 25 } },
3777 { ISD::CTLZ, MVT::v4i64, { 14, 18, 24, 44 } },
3778 { ISD::CTLZ, MVT::v4i32, { 5, 16, 19, 20 } },
3779 { ISD::CTLZ, MVT::v8i32, { 10, 16, 19, 34 } },
3780 { ISD::CTLZ, MVT::v8i16, { 4, 13, 14, 15 } },
3781 { ISD::CTLZ, MVT::v16i16, { 6, 14, 14, 24 } },
3782 { ISD::CTLZ, MVT::v16i8, { 3, 12, 9, 10 } },
3783 { ISD::CTLZ, MVT::v32i8, { 4, 12, 9, 14 } },
3784 { ISD::CTPOP, MVT::v2i64, { 3, 9, 10, 10 } },
3785 { ISD::CTPOP, MVT::v4i64, { 4, 9, 10, 14 } },
3786 { ISD::CTPOP, MVT::v4i32, { 7, 12, 14, 14 } },
3787 { ISD::CTPOP, MVT::v8i32, { 7, 12, 14, 18 } },
3788 { ISD::CTPOP, MVT::v8i16, { 3, 7, 11, 11 } },
3789 { ISD::CTPOP, MVT::v16i16, { 6, 8, 11, 18 } },
3790 { ISD::CTPOP, MVT::v16i8, { 2, 5, 8, 8 } },
3791 { ISD::CTPOP, MVT::v32i8, { 3, 5, 8, 12 } },
3792 { ISD::CTTZ, MVT::v2i64, { 4, 11, 13, 13 } },
3793 { ISD::CTTZ, MVT::v4i64, { 5, 11, 13, 20 } },
3794 { ISD::CTTZ, MVT::v4i32, { 7, 14, 17, 17 } },
3795 { ISD::CTTZ, MVT::v8i32, { 7, 15, 17, 24 } },
3796 { ISD::CTTZ, MVT::v8i16, { 4, 9, 14, 14 } },
3797 { ISD::CTTZ, MVT::v16i16, { 6, 9, 14, 24 } },
3798 { ISD::CTTZ, MVT::v16i8, { 3, 7, 11, 11 } },
3799 { ISD::CTTZ, MVT::v32i8, { 5, 7, 11, 18 } },
3800 { ISD::SADDSAT, MVT::v16i16, { 1 } },
3801 { ISD::SADDSAT, MVT::v32i8, { 1 } },
3802 { ISD::SMAX, MVT::v2i64, { 2, 7, 2, 3 } },
3803 { ISD::SMAX, MVT::v4i64, { 2, 7, 2, 3 } },
3804 { ISD::SMAX, MVT::v8i32, { 1, 1, 1, 2 } },
3805 { ISD::SMAX, MVT::v16i16, { 1, 1, 1, 2 } },
3806 { ISD::SMAX, MVT::v32i8, { 1, 1, 1, 2 } },
3807 { ISD::SMIN, MVT::v2i64, { 2, 7, 2, 3 } },
3808 { ISD::SMIN, MVT::v4i64, { 2, 7, 2, 3 } },
3809 { ISD::SMIN, MVT::v8i32, { 1, 1, 1, 2 } },
3810 { ISD::SMIN, MVT::v16i16, { 1, 1, 1, 2 } },
3811 { ISD::SMIN, MVT::v32i8, { 1, 1, 1, 2 } },
3812 { ISD::SSUBSAT, MVT::v16i16, { 1 } },
3813 { ISD::SSUBSAT, MVT::v32i8, { 1 } },
3814 { ISD::UADDSAT, MVT::v16i16, { 1 } },
3815 { ISD::UADDSAT, MVT::v32i8, { 1 } },
3816 { ISD::UADDSAT, MVT::v8i32, { 3 } }, // not + pminud + paddd
3817 { ISD::UMAX, MVT::v2i64, { 2, 8, 5, 6 } },
3818 { ISD::UMAX, MVT::v4i64, { 2, 8, 5, 8 } },
3819 { ISD::UMAX, MVT::v8i32, { 1, 1, 1, 2 } },
3820 { ISD::UMAX, MVT::v16i16, { 1, 1, 1, 2 } },
3821 { ISD::UMAX, MVT::v32i8, { 1, 1, 1, 2 } },
3822 { ISD::UMIN, MVT::v2i64, { 2, 8, 5, 6 } },
3823 { ISD::UMIN, MVT::v4i64, { 2, 8, 5, 8 } },
3824 { ISD::UMIN, MVT::v8i32, { 1, 1, 1, 2 } },
3825 { ISD::UMIN, MVT::v16i16, { 1, 1, 1, 2 } },
3826 { ISD::UMIN, MVT::v32i8, { 1, 1, 1, 2 } },
3827 { ISD::USUBSAT, MVT::v16i16, { 1 } },
3828 { ISD::USUBSAT, MVT::v32i8, { 1 } },
3829 { ISD::USUBSAT, MVT::v8i32, { 2 } }, // pmaxud + psubd
3830 { ISD::FMAXNUM, MVT::f32, { 2, 7, 3, 5 } }, // MAXSS + CMPUNORDSS + BLENDVPS
3831 { ISD::FMAXNUM, MVT::v4f32, { 2, 7, 3, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3832 { ISD::FMAXNUM, MVT::v8f32, { 3, 7, 3, 6 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3833 { ISD::FMAXNUM, MVT::f64, { 2, 7, 3, 5 } }, // MAXSD + CMPUNORDSD + BLENDVPD
3834 { ISD::FMAXNUM, MVT::v2f64, { 2, 7, 3, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3835 { ISD::FMAXNUM, MVT::v4f64, { 3, 7, 3, 6 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3836 { ISD::FSQRT, MVT::f32, { 7, 15, 1, 1 } }, // vsqrtss
3837 { ISD::FSQRT, MVT::v4f32, { 7, 15, 1, 1 } }, // vsqrtps
3838 { ISD::FSQRT, MVT::v8f32, { 14, 21, 1, 3 } }, // vsqrtps
3839 { ISD::FSQRT, MVT::f64, { 14, 21, 1, 1 } }, // vsqrtsd
3840 { ISD::FSQRT, MVT::v2f64, { 14, 21, 1, 1 } }, // vsqrtpd
3841 { ISD::FSQRT, MVT::v4f64, { 28, 35, 1, 3 } }, // vsqrtpd
3844 { ISD::ABS, MVT::v4i64, { 6, 8, 6, 12 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
3845 { ISD::ABS, MVT::v8i32, { 3, 6, 4, 5 } },
3846 { ISD::ABS, MVT::v16i16, { 3, 6, 4, 5 } },
3847 { ISD::ABS, MVT::v32i8, { 3, 6, 4, 5 } },
3848 { ISD::BITREVERSE, MVT::v4i64, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
3849 { ISD::BITREVERSE, MVT::v2i64, { 8, 13, 10, 16 } },
3850 { ISD::BITREVERSE, MVT::v8i32, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
3851 { ISD::BITREVERSE, MVT::v4i32, { 8, 13, 10, 16 } },
3852 { ISD::BITREVERSE, MVT::v16i16, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
3853 { ISD::BITREVERSE, MVT::v8i16, { 8, 13, 10, 16 } },
3854 { ISD::BITREVERSE, MVT::v32i8, { 13, 15, 17, 26 } }, // 2 x 128-bit Op + extract/insert
3855 { ISD::BITREVERSE, MVT::v16i8, { 7, 7, 9, 13 } },
3856 { ISD::BSWAP, MVT::v4i64, { 5, 6, 5, 10 } },
3857 { ISD::BSWAP, MVT::v2i64, { 2, 2, 1, 3 } },
3858 { ISD::BSWAP, MVT::v8i32, { 5, 6, 5, 10 } },
3859 { ISD::BSWAP, MVT::v4i32, { 2, 2, 1, 3 } },
3860 { ISD::BSWAP, MVT::v16i16, { 5, 6, 5, 10 } },
3861 { ISD::BSWAP, MVT::v8i16, { 2, 2, 1, 3 } },
3862 { ISD::CTLZ, MVT::v4i64, { 29, 33, 49, 58 } }, // 2 x 128-bit Op + extract/insert
3863 { ISD::CTLZ, MVT::v2i64, { 14, 24, 24, 28 } },
3864 { ISD::CTLZ, MVT::v8i32, { 24, 28, 39, 48 } }, // 2 x 128-bit Op + extract/insert
3865 { ISD::CTLZ, MVT::v4i32, { 12, 20, 19, 23 } },
3866 { ISD::CTLZ, MVT::v16i16, { 19, 22, 29, 38 } }, // 2 x 128-bit Op + extract/insert
3867 { ISD::CTLZ, MVT::v8i16, { 9, 16, 14, 18 } },
3868 { ISD::CTLZ, MVT::v32i8, { 14, 15, 19, 28 } }, // 2 x 128-bit Op + extract/insert
3869 { ISD::CTLZ, MVT::v16i8, { 7, 12, 9, 13 } },
3870 { ISD::CTPOP, MVT::v4i64, { 14, 18, 19, 28 } }, // 2 x 128-bit Op + extract/insert
3871 { ISD::CTPOP, MVT::v2i64, { 7, 14, 10, 14 } },
3872 { ISD::CTPOP, MVT::v8i32, { 18, 24, 27, 36 } }, // 2 x 128-bit Op + extract/insert
3873 { ISD::CTPOP, MVT::v4i32, { 9, 20, 14, 18 } },
3874 { ISD::CTPOP, MVT::v16i16, { 16, 21, 22, 31 } }, // 2 x 128-bit Op + extract/insert
3875 { ISD::CTPOP, MVT::v8i16, { 8, 18, 11, 15 } },
3876 { ISD::CTPOP, MVT::v32i8, { 13, 15, 16, 25 } }, // 2 x 128-bit Op + extract/insert
3877 { ISD::CTPOP, MVT::v16i8, { 6, 12, 8, 12 } },
3878 { ISD::CTTZ, MVT::v4i64, { 17, 22, 24, 33 } }, // 2 x 128-bit Op + extract/insert
3879 { ISD::CTTZ, MVT::v2i64, { 9, 19, 13, 17 } },
3880 { ISD::CTTZ, MVT::v8i32, { 21, 27, 32, 41 } }, // 2 x 128-bit Op + extract/insert
3881 { ISD::CTTZ, MVT::v4i32, { 11, 24, 17, 21 } },
3882 { ISD::CTTZ, MVT::v16i16, { 18, 24, 27, 36 } }, // 2 x 128-bit Op + extract/insert
3883 { ISD::CTTZ, MVT::v8i16, { 9, 21, 14, 18 } },
3884 { ISD::CTTZ, MVT::v32i8, { 15, 18, 21, 30 } }, // 2 x 128-bit Op + extract/insert
3885 { ISD::CTTZ, MVT::v16i8, { 8, 16, 11, 15 } },
3886 { ISD::SADDSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert
3887 { ISD::SADDSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert
3888 { ISD::SMAX, MVT::v4i64, { 6, 9, 6, 12 } }, // 2 x 128-bit Op + extract/insert
3889 { ISD::SMAX, MVT::v2i64, { 3, 7, 2, 4 } },
3890 { ISD::SMAX, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3891 { ISD::SMAX, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3892 { ISD::SMAX, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3893 { ISD::SMIN, MVT::v4i64, { 6, 9, 6, 12 } }, // 2 x 128-bit Op + extract/insert
3894 { ISD::SMIN, MVT::v2i64, { 3, 7, 2, 3 } },
3895 { ISD::SMIN, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3896 { ISD::SMIN, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3897 { ISD::SMIN, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3898 { ISD::SSUBSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert
3899 { ISD::SSUBSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert
3900 { ISD::UADDSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert
3901 { ISD::UADDSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert
3902 { ISD::UADDSAT, MVT::v8i32, { 8 } }, // 2 x 128-bit Op + extract/insert
3903 { ISD::UMAX, MVT::v4i64, { 9, 10, 11, 17 } }, // 2 x 128-bit Op + extract/insert
3904 { ISD::UMAX, MVT::v2i64, { 4, 8, 5, 7 } },
3905 { ISD::UMAX, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3906 { ISD::UMAX, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3907 { ISD::UMAX, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3908 { ISD::UMIN, MVT::v4i64, { 9, 10, 11, 17 } }, // 2 x 128-bit Op + extract/insert
3909 { ISD::UMIN, MVT::v2i64, { 4, 8, 5, 7 } },
3910 { ISD::UMIN, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3911 { ISD::UMIN, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3912 { ISD::UMIN, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
3913 { ISD::USUBSAT, MVT::v16i16, { 4 } }, // 2 x 128-bit Op + extract/insert
3914 { ISD::USUBSAT, MVT::v32i8, { 4 } }, // 2 x 128-bit Op + extract/insert
3915 { ISD::USUBSAT, MVT::v8i32, { 6 } }, // 2 x 128-bit Op + extract/insert
3916 { ISD::FMAXNUM, MVT::f32, { 3, 6, 3, 5 } }, // MAXSS + CMPUNORDSS + BLENDVPS
3917 { ISD::FMAXNUM, MVT::v4f32, { 3, 6, 3, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3918 { ISD::FMAXNUM, MVT::v8f32, { 5, 7, 3, 10 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3919 { ISD::FMAXNUM, MVT::f64, { 3, 6, 3, 5 } }, // MAXSD + CMPUNORDSD + BLENDVPD
3920 { ISD::FMAXNUM, MVT::v2f64, { 3, 6, 3, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3921 { ISD::FMAXNUM, MVT::v4f64, { 5, 7, 3, 10 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3922 { ISD::FSQRT, MVT::f32, { 21, 21, 1, 1 } }, // vsqrtss
3923 { ISD::FSQRT, MVT::v4f32, { 21, 21, 1, 1 } }, // vsqrtps
3924 { ISD::FSQRT, MVT::v8f32, { 42, 42, 1, 3 } }, // vsqrtps
3925 { ISD::FSQRT, MVT::f64, { 27, 27, 1, 1 } }, // vsqrtsd
3926 { ISD::FSQRT, MVT::v2f64, { 27, 27, 1, 1 } }, // vsqrtpd
3927 { ISD::FSQRT, MVT::v4f64, { 54, 54, 1, 3 } }, // vsqrtpd
3930 { ISD::BITREVERSE, MVT::i8, { 3, 3, 3, 4 } }, // gf2p8affineqb
3931 { ISD::BITREVERSE, MVT::i16, { 3, 3, 4, 6 } }, // gf2p8affineqb
3932 { ISD::BITREVERSE, MVT::i32, { 3, 3, 4, 5 } }, // gf2p8affineqb
3933 { ISD::BITREVERSE, MVT::i64, { 3, 3, 4, 6 } }, // gf2p8affineqb
3934 { ISD::BITREVERSE, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
3935 { ISD::BITREVERSE, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
3936 { ISD::BITREVERSE, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
3937 { ISD::BITREVERSE, MVT::v8i16, { 1, 8, 2, 4 } }, // gf2p8affineqb
3938 { ISD::BITREVERSE, MVT::v16i16, { 1, 9, 2, 4 } }, // gf2p8affineqb
3939 { ISD::BITREVERSE, MVT::v32i16, { 1, 9, 2, 4 } }, // gf2p8affineqb
3940 { ISD::BITREVERSE, MVT::v4i32, { 1, 8, 2, 4 } }, // gf2p8affineqb
3941 { ISD::BITREVERSE, MVT::v8i32, { 1, 9, 2, 4 } }, // gf2p8affineqb
3942 { ISD::BITREVERSE, MVT::v16i32, { 1, 9, 2, 4 } }, // gf2p8affineqb
3943 { ISD::BITREVERSE, MVT::v2i64, { 1, 8, 2, 4 } }, // gf2p8affineqb
3944 { ISD::BITREVERSE, MVT::v4i64, { 1, 9, 2, 4 } }, // gf2p8affineqb
3945 { ISD::BITREVERSE, MVT::v8i64, { 1, 9, 2, 4 } }, // gf2p8affineqb
3951 { ISD::FSQRT, MVT::f32, { 19, 20, 1, 1 } }, // sqrtss
3952 { ISD::FSQRT, MVT::v4f32, { 37, 41, 1, 5 } }, // sqrtps
3953 { ISD::FSQRT, MVT::f64, { 34, 35, 1, 1 } }, // sqrtsd
3954 { ISD::FSQRT, MVT::v2f64, { 67, 71, 1, 5 } }, // sqrtpd
3957 { ISD::BSWAP, MVT::v2i64, { 5, 5, 1, 5 } },
3958 { ISD::BSWAP, MVT::v4i32, { 5, 5, 1, 5 } },
3959 { ISD::BSWAP, MVT::v8i16, { 5, 5, 1, 5 } },
3960 { ISD::FSQRT, MVT::f32, { 20, 20, 1, 1 } }, // sqrtss
3961 { ISD::FSQRT, MVT::v4f32, { 40, 41, 1, 5 } }, // sqrtps
3962 { ISD::FSQRT, MVT::f64, { 35, 35, 1, 1 } }, // sqrtsd
3963 { ISD::FSQRT, MVT::v2f64, { 70, 71, 1, 5 } }, // sqrtpd
3966 { ISD::USUBSAT, MVT::v4i32, { 2 } }, // pmaxud + psubd
3967 { ISD::UADDSAT, MVT::v4i32, { 3 } }, // not + pminud + paddd
3968 { ISD::FMAXNUM, MVT::f32, { 5, 5, 7, 7 } }, // MAXSS + CMPUNORDSS + BLENDVPS
3969 { ISD::FMAXNUM, MVT::v4f32, { 4, 4, 4, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
3970 { ISD::FMAXNUM, MVT::f64, { 5, 5, 7, 7 } }, // MAXSD + CMPUNORDSD + BLENDVPD
3971 { ISD::FMAXNUM, MVT::v2f64, { 4, 4, 4, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
3972 { ISD::FSQRT, MVT::f32, { 18, 18, 1, 1 } }, // Nehalem from http://www.agner.org/
3973 { ISD::FSQRT, MVT::v4f32, { 18, 18, 1, 1 } }, // Nehalem from http://www.agner.org/
3976 { ISD::ABS, MVT::v2i64, { 3, 4, 3, 5 } }, // BLENDVPD(X,PSUBQ(0,X),X)
3977 { ISD::SMAX, MVT::v2i64, { 3, 7, 2, 3 } },
3978 { ISD::SMAX, MVT::v4i32, { 1, 1, 1, 1 } },
3979 { ISD::SMAX, MVT::v16i8, { 1, 1, 1, 1 } },
3980 { ISD::SMIN, MVT::v2i64, { 3, 7, 2, 3 } },
3981 { ISD::SMIN, MVT::v4i32, { 1, 1, 1, 1 } },
3982 { ISD::SMIN, MVT::v16i8, { 1, 1, 1, 1 } },
3983 { ISD::UMAX, MVT::v2i64, { 2, 11, 6, 7 } },
3984 { ISD::UMAX, MVT::v4i32, { 1, 1, 1, 1 } },
3985 { ISD::UMAX, MVT::v8i16, { 1, 1, 1, 1 } },
3986 { ISD::UMIN, MVT::v2i64, { 2, 11, 6, 7 } },
3987 { ISD::UMIN, MVT::v4i32, { 1, 1, 1, 1 } },
3988 { ISD::UMIN, MVT::v8i16, { 1, 1, 1, 1 } },
3991 { ISD::ABS, MVT::v4i32, { 1, 2, 1, 1 } },
3992 { ISD::ABS, MVT::v8i16, { 1, 2, 1, 1 } },
3993 { ISD::ABS, MVT::v16i8, { 1, 2, 1, 1 } },
3994 { ISD::BITREVERSE, MVT::v2i64, { 16, 20, 11, 21 } },
3995 { ISD::BITREVERSE, MVT::v4i32, { 16, 20, 11, 21 } },
3996 { ISD::BITREVERSE, MVT::v8i16, { 16, 20, 11, 21 } },
3997 { ISD::BITREVERSE, MVT::v16i8, { 11, 12, 10, 16 } },
3998 { ISD::BSWAP, MVT::v2i64, { 2, 3, 1, 5 } },
3999 { ISD::BSWAP, MVT::v4i32, { 2, 3, 1, 5 } },
4000 { ISD::BSWAP, MVT::v8i16, { 2, 3, 1, 5 } },
4001 { ISD::CTLZ, MVT::v2i64, { 18, 28, 28, 35 } },
4002 { ISD::CTLZ, MVT::v4i32, { 15, 20, 22, 28 } },
4003 { ISD::CTLZ, MVT::v8i16, { 13, 17, 16, 22 } },
4004 { ISD::CTLZ, MVT::v16i8, { 11, 15, 10, 16 } },
4005 { ISD::CTPOP, MVT::v2i64, { 13, 19, 12, 18 } },
4006 { ISD::CTPOP, MVT::v4i32, { 18, 24, 16, 22 } },
4007 { ISD::CTPOP, MVT::v8i16, { 13, 18, 14, 20 } },
4008 { ISD::CTPOP, MVT::v16i8, { 11, 12, 10, 16 } },
4009 { ISD::CTTZ, MVT::v2i64, { 13, 25, 15, 22 } },
4010 { ISD::CTTZ, MVT::v4i32, { 18, 26, 19, 25 } },
4011 { ISD::CTTZ, MVT::v8i16, { 13, 20, 17, 23 } },
4012 { ISD::CTTZ, MVT::v16i8, { 11, 16, 13, 19 } }
4015 { ISD::ABS, MVT::v2i64, { 3, 6, 5, 5 } },
4016 { ISD::ABS, MVT::v4i32, { 1, 4, 4, 4 } },
4017 { ISD::ABS, MVT::v8i16, { 1, 2, 3, 3 } },
4018 { ISD::ABS, MVT::v16i8, { 1, 2, 3, 3 } },
4019 { ISD::BITREVERSE, MVT::v2i64, { 16, 20, 32, 32 } },
4020 { ISD::BITREVERSE, MVT::v4i32, { 16, 20, 30, 30 } },
4021 { ISD::BITREVERSE, MVT::v8i16, { 16, 20, 25, 25 } },
4022 { ISD::BITREVERSE, MVT::v16i8, { 11, 12, 21, 21 } },
4023 { ISD::BSWAP, MVT::v2i64, { 5, 6, 11, 11 } },
4024 { ISD::BSWAP, MVT::v4i32, { 5, 5, 9, 9 } },
4025 { ISD::BSWAP, MVT::v8i16, { 5, 5, 4, 5 } },
4026 { ISD::CTLZ, MVT::v2i64, { 10, 45, 36, 38 } },
4027 { ISD::CTLZ, MVT::v4i32, { 10, 45, 38, 40 } },
4028 { ISD::CTLZ, MVT::v8i16, { 9, 38, 32, 34 } },
4029 { ISD::CTLZ, MVT::v16i8, { 8, 39, 29, 32 } },
4030 { ISD::CTPOP, MVT::v2i64, { 12, 26, 16, 18 } },
4031 { ISD::CTPOP, MVT::v4i32, { 15, 29, 21, 23 } },
4032 { ISD::CTPOP, MVT::v8i16, { 13, 25, 18, 20 } },
4033 { ISD::CTPOP, MVT::v16i8, { 10, 21, 14, 16 } },
4034 { ISD::CTTZ, MVT::v2i64, { 14, 28, 19, 21 } },
4035 { ISD::CTTZ, MVT::v4i32, { 18, 31, 24, 26 } },
4036 { ISD::CTTZ, MVT::v8i16, { 16, 27, 21, 23 } },
4037 { ISD::CTTZ, MVT::v16i8, { 13, 23, 17, 19 } },
4038 { ISD::SADDSAT, MVT::v8i16, { 1 } },
4039 { ISD::SADDSAT, MVT::v16i8, { 1 } },
4040 { ISD::SMAX, MVT::v2i64, { 4, 8, 15, 15 } },
4041 { ISD::SMAX, MVT::v4i32, { 2, 4, 5, 5 } },
4042 { ISD::SMAX, MVT::v8i16, { 1, 1, 1, 1 } },
4043 { ISD::SMAX, MVT::v16i8, { 2, 4, 5, 5 } },
4044 { ISD::SMIN, MVT::v2i64, { 4, 8, 15, 15 } },
4045 { ISD::SMIN, MVT::v4i32, { 2, 4, 5, 5 } },
4046 { ISD::SMIN, MVT::v8i16, { 1, 1, 1, 1 } },
4047 { ISD::SMIN, MVT::v16i8, { 2, 4, 5, 5 } },
4048 { ISD::SSUBSAT, MVT::v8i16, { 1 } },
4049 { ISD::SSUBSAT, MVT::v16i8, { 1 } },
4050 { ISD::UADDSAT, MVT::v8i16, { 1 } },
4051 { ISD::UADDSAT, MVT::v16i8, { 1 } },
4052 { ISD::UMAX, MVT::v2i64, { 4, 8, 15, 15 } },
4053 { ISD::UMAX, MVT::v4i32, { 2, 5, 8, 8 } },
4054 { ISD::UMAX, MVT::v8i16, { 1, 3, 3, 3 } },
4055 { ISD::UMAX, MVT::v16i8, { 1, 1, 1, 1 } },
4056 { ISD::UMIN, MVT::v2i64, { 4, 8, 15, 15 } },
4057 { ISD::UMIN, MVT::v4i32, { 2, 5, 8, 8 } },
4058 { ISD::UMIN, MVT::v8i16, { 1, 3, 3, 3 } },
4059 { ISD::UMIN, MVT::v16i8, { 1, 1, 1, 1 } },
4060 { ISD::USUBSAT, MVT::v8i16, { 1 } },
4061 { ISD::USUBSAT, MVT::v16i8, { 1 } },
4062 { ISD::FMAXNUM, MVT::f64, { 5, 5, 7, 7 } },
4063 { ISD::FMAXNUM, MVT::v2f64, { 4, 6, 6, 6 } },
4064 { ISD::FSQRT, MVT::f64, { 32, 32, 1, 1 } }, // Nehalem from http://www.agner.org/
4065 { ISD::FSQRT, MVT::v2f64, { 32, 32, 1, 1 } }, // Nehalem from http://www.agner.org/
4068 { ISD::FMAXNUM, MVT::f32, { 5, 5, 7, 7 } },
4069 { ISD::FMAXNUM, MVT::v4f32, { 4, 6, 6, 6 } },
4070 { ISD::FSQRT, MVT::f32, { 28, 30, 1, 2 } }, // Pentium III from http://www.agner.org/
4071 { ISD::FSQRT, MVT::v4f32, { 56, 56, 1, 2 } }, // Pentium III from http://www.agner.org/
4074 { ISD::CTTZ, MVT::i64, { 1 } },
4077 { ISD::CTTZ, MVT::i32, { 1 } },
4078 { ISD::CTTZ, MVT::i16, { 1 } },
4079 { ISD::CTTZ, MVT::i8, { 1 } },
4082 { ISD::CTLZ, MVT::i64, { 1 } },
4085 { ISD::CTLZ, MVT::i32, { 1 } },
4086 { ISD::CTLZ, MVT::i16, { 2 } },
4087 { ISD::CTLZ, MVT::i8, { 2 } },
4090 { ISD::CTPOP, MVT::i64, { 1, 1, 1, 1 } }, // popcnt
4093 { ISD::CTPOP, MVT::i32, { 1, 1, 1, 1 } }, // popcnt
4094 { ISD::CTPOP, MVT::i16, { 1, 1, 2, 2 } }, // popcnt(zext())
4095 { ISD::CTPOP, MVT::i8, { 1, 1, 2, 2 } }, // popcnt(zext())
4098 { ISD::ABS, MVT::i64, { 1, 2, 3, 3 } }, // SUB+CMOV
4099 { ISD::BITREVERSE, MVT::i64, { 10, 12, 20, 22 } },
4100 { ISD::BSWAP, MVT::i64, { 1, 2, 1, 2 } },
4101 { ISD::CTLZ, MVT::i64, { 4 } }, // BSR+XOR or BSR+XOR+CMOV
4102 { ISD::CTLZ_ZERO_UNDEF, MVT::i64,{ 1, 1, 1, 1 } }, // BSR+XOR
4103 { ISD::CTTZ, MVT::i64, { 3 } }, // TEST+BSF+CMOV/BRANCH
4104 { ISD::CTTZ_ZERO_UNDEF, MVT::i64,{ 1, 1, 1, 1 } }, // BSR
4105 { ISD::CTPOP, MVT::i64, { 10, 6, 19, 19 } },
4106 { ISD::ROTL, MVT::i64, { 2, 3, 1, 3 } },
4107 { ISD::ROTR, MVT::i64, { 2, 3, 1, 3 } },
4109 { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } },
4110 { ISD::SMAX, MVT::i64, { 1, 3, 2, 3 } },
4111 { ISD::SMIN, MVT::i64, { 1, 3, 2, 3 } },
4112 { ISD::UMAX, MVT::i64, { 1, 3, 2, 3 } },
4113 { ISD::UMIN, MVT::i64, { 1, 3, 2, 3 } },
4114 { ISD::SADDO, MVT::i64, { 1 } },
4115 { ISD::UADDO, MVT::i64, { 1 } },
4116 { ISD::UMULO, MVT::i64, { 2 } }, // mulq + seto
4119 { ISD::ABS, MVT::i32, { 1, 2, 3, 3 } }, // SUB+XOR+SRA or SUB+CMOV
4120 { ISD::ABS, MVT::i16, { 2, 2, 3, 3 } }, // SUB+XOR+SRA or SUB+CMOV
4121 { ISD::ABS, MVT::i8, { 2, 4, 4, 3 } }, // SUB+XOR+SRA
4122 { ISD::BITREVERSE, MVT::i32, { 9, 12, 17, 19 } },
4123 { ISD::BITREVERSE, MVT::i16, { 9, 12, 17, 19 } },
4124 { ISD::BITREVERSE, MVT::i8, { 7, 9, 13, 14 } },
4125 { ISD::BSWAP, MVT::i32, { 1, 1, 1, 1 } },
4126 { ISD::BSWAP, MVT::i16, { 1, 2, 1, 2 } }, // ROL
4127 { ISD::CTLZ, MVT::i32, { 4 } }, // BSR+XOR or BSR+XOR+CMOV
4128 { ISD::CTLZ, MVT::i16, { 4 } }, // BSR+XOR or BSR+XOR+CMOV
4129 { ISD::CTLZ, MVT::i8, { 4 } }, // BSR+XOR or BSR+XOR+CMOV
4130 { ISD::CTLZ_ZERO_UNDEF, MVT::i32,{ 1, 1, 1, 1 } }, // BSR+XOR
4131 { ISD::CTLZ_ZERO_UNDEF, MVT::i16,{ 2, 2, 3, 3 } }, // BSR+XOR
4132 { ISD::CTLZ_ZERO_UNDEF, MVT::i8, { 2, 2, 3, 3 } }, // BSR+XOR
4133 { ISD::CTTZ, MVT::i32, { 3 } }, // TEST+BSF+CMOV/BRANCH
4134 { ISD::CTTZ, MVT::i16, { 3 } }, // TEST+BSF+CMOV/BRANCH
4135 { ISD::CTTZ, MVT::i8, { 3 } }, // TEST+BSF+CMOV/BRANCH
4136 { ISD::CTTZ_ZERO_UNDEF, MVT::i32,{ 1, 1, 1, 1 } }, // BSF
4137 { ISD::CTTZ_ZERO_UNDEF, MVT::i16,{ 2, 2, 1, 1 } }, // BSF
4138 { ISD::CTTZ_ZERO_UNDEF, MVT::i8, { 2, 2, 1, 1 } }, // BSF
4139 { ISD::CTPOP, MVT::i32, { 8, 7, 15, 15 } },
4140 { ISD::CTPOP, MVT::i16, { 9, 8, 17, 17 } },
4141 { ISD::CTPOP, MVT::i8, { 7, 6, 6, 6 } },
4142 { ISD::ROTL, MVT::i32, { 2, 3, 1, 3 } },
4143 { ISD::ROTL, MVT::i16, { 2, 3, 1, 3 } },
4144 { ISD::ROTL, MVT::i8, { 2, 3, 1, 3 } },
4145 { ISD::ROTR, MVT::i32, { 2, 3, 1, 3 } },
4146 { ISD::ROTR, MVT::i16, { 2, 3, 1, 3 } },
4147 { ISD::ROTR, MVT::i8, { 2, 3, 1, 3 } },
4151 { ISD::FSHL, MVT::i32, { 4, 4, 1, 4 } },
4152 { ISD::FSHL, MVT::i16, { 4, 4, 2, 5 } },
4153 { ISD::FSHL, MVT::i8, { 4, 4, 2, 5 } },
4154 { ISD::SMAX, MVT::i32, { 1, 2, 2, 3 } },
4155 { ISD::SMAX, MVT::i16, { 1, 4, 2, 4 } },
4156 { ISD::SMAX, MVT::i8, { 1, 4, 2, 4 } },
4157 { ISD::SMIN, MVT::i32, { 1, 2, 2, 3 } },
4158 { ISD::SMIN, MVT::i16, { 1, 4, 2, 4 } },
4159 { ISD::SMIN, MVT::i8, { 1, 4, 2, 4 } },
4160 { ISD::UMAX, MVT::i32, { 1, 2, 2, 3 } },
4161 { ISD::UMAX, MVT::i16, { 1, 4, 2, 4 } },
4162 { ISD::UMAX, MVT::i8, { 1, 4, 2, 4 } },
4163 { ISD::UMIN, MVT::i32, { 1, 2, 2, 3 } },
4164 { ISD::UMIN, MVT::i16, { 1, 4, 2, 4 } },
4165 { ISD::UMIN, MVT::i8, { 1, 4, 2, 4 } },
4166 { ISD::SADDO, MVT::i32, { 1 } },
4167 { ISD::SADDO, MVT::i16, { 1 } },
4168 { ISD::SADDO, MVT::i8, { 1 } },
4169 { ISD::UADDO, MVT::i32, { 1 } },
4170 { ISD::UADDO, MVT::i16, { 1 } },
4171 { ISD::UADDO, MVT::i8, { 1 } },
4172 { ISD::UMULO, MVT::i32, { 2 } }, // mul + seto
4173 { ISD::UMULO, MVT::i16, { 2 } },
4174 { ISD::UMULO, MVT::i8, { 2 } },
4180 unsigned ISD = ISD::DELETED_NODE;
4185 ISD = ISD::ABS;
4188 ISD = ISD::BITREVERSE;
4191 ISD = ISD::BSWAP;
4194 ISD = ISD::CTLZ;
4197 ISD = ISD::CTPOP;
4200 ISD = ISD::CTTZ;
4203 ISD = ISD::FSHL;
4207 ISD = ISD::ROTL;
4213 ISD = X86ISD::VROTLI;
4219 ISD = ISD::FSHL;
4223 ISD = ISD::ROTR;
4229 ISD = X86ISD::VROTLI;
4246 ISD = ISD::FMAXNUM;
4249 ISD = ISD::SADDSAT;
4252 ISD = ISD::SMAX;
4255 ISD = ISD::SMIN;
4258 ISD = ISD::SSUBSAT;
4261 ISD = ISD::UADDSAT;
4264 ISD = ISD::UMAX;
4267 ISD = ISD::UMIN;
4270 ISD = ISD::USUBSAT;
4273 ISD = ISD::FSQRT;
4278 ISD = ISD::SADDO;
4284 ISD = ISD::UADDO;
4290 ISD = ISD::UMULO;
4295 if (ISD != ISD::DELETED_NODE) {
4296 auto adjustTableCost = [&](int ISD, unsigned Cost,
4305 if (ISD == ISD::FMAXNUM || ISD == ISD::FMINNUM) {
4312 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) {
4332 if (((ISD == ISD::CTTZ && !ST->hasBMI()) ||
4333 (ISD == ISD::CTLZ && !ST->hasLZCNT())) &&
4338 ISD = ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_UNDEF : ISD::CTLZ_ZERO_UNDEF;
4342 if (ISD == ISD::FSQRT && CostKind == TTI::TCK_CodeSize)
4346 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy))
4348 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4351 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
4353 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4356 if (const auto *Entry = CostTableLookup(AVX512VBMI2CostTbl, ISD, MTy))
4358 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4361 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy))
4363 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4366 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy))
4368 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4371 if (const auto *Entry = CostTableLookup(GFNICostTbl, ISD, MTy))
4373 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4376 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
4378 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4381 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
4383 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4386 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
4388 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4391 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
4393 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4396 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
4398 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4401 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
4403 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4406 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
4408 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4411 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
4413 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4416 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
4418 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4421 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
4423 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4426 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
4428 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4432 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy))
4434 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4436 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy))
4438 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4443 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy))
4445 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4447 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy))
4449 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4454 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy))
4456 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4458 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy))
4460 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4464 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
4466 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4468 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
4470 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4481 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 },
4482 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 },
4483 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 },
4484 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 }
4589 int ISD = TLI->InstructionOpcodeToISD(Opcode);
4590 assert(ISD && "Unexpected vector opcode");
4592 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy))
4643 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much
4644 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT.
5184 { ISD::FADD, MVT::v2f64, 3 },
5185 { ISD::ADD, MVT::v2i64, 5 },
5189 { ISD::FADD, MVT::v2f64, 2 },
5190 { ISD::FADD, MVT::v2f32, 2 },
5191 { ISD::FADD, MVT::v4f32, 4 },
5192 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
5193 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32
5194 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
5195 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3".
5196 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3".
5197 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
5198 { ISD::ADD, MVT::v2i8, 2 },
5199 { ISD::ADD, MVT::v4i8, 2 },
5200 { ISD::ADD, MVT::v8i8, 2 },
5201 { ISD::ADD, MVT::v16i8, 3 },
5205 { ISD::FADD, MVT::v4f64, 3 },
5206 { ISD::FADD, MVT::v4f32, 3 },
5207 { ISD::FADD, MVT::v8f32, 4 },
5208 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
5209 { ISD::ADD, MVT::v4i64, 3 },
5210 { ISD::ADD, MVT::v8i32, 5 },
5211 { ISD::ADD, MVT::v16i16, 5 },
5212 { ISD::ADD, MVT::v32i8, 4 },
5215 int ISD = TLI->InstructionOpcodeToISD(Opcode);
5216 assert(ISD && "Invalid opcode");
5225 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
5229 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5233 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5244 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) {
5264 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
5268 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5272 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5278 { ISD::AND, MVT::v2i1, 3 },
5279 { ISD::AND, MVT::v4i1, 5 },
5280 { ISD::AND, MVT::v8i1, 7 },
5281 { ISD::AND, MVT::v16i1, 9 },
5282 { ISD::AND, MVT::v32i1, 11 },
5283 { ISD::AND, MVT::v64i1, 13 },
5284 { ISD::OR, MVT::v2i1, 3 },
5285 { ISD::OR, MVT::v4i1, 5 },
5286 { ISD::OR, MVT::v8i1, 7 },
5287 { ISD::OR, MVT::v16i1, 9 },
5288 { ISD::OR, MVT::v32i1, 11 },
5289 { ISD::OR, MVT::v64i1, 13 },
5293 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp
5294 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp
5295 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp
5296 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp
5300 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp
5301 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp
5302 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
5303 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
5304 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp
5305 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp
5306 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
5307 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
5311 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp
5312 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp
5313 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp
5314 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp
5315 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp
5316 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp
5317 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp
5318 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp
5334 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy))
5337 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy))
5340 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy))
5343 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy))
5439 int ISD;
5441 ISD = (IID == Intrinsic::umin || IID == Intrinsic::umax) ? ISD::UMIN
5442 : ISD::SMIN;
5446 ISD = (IID == Intrinsic::minnum || IID == Intrinsic::maxnum)
5447 ? ISD::FMINNUM
5448 : ISD::FMINIMUM;
5455 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw
5456 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw
5457 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw
5461 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2
5462 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2
5463 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2
5464 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2
5465 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor
5466 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax
5467 {ISD::SMIN, MVT::v2i8, 3}, // pminsb
5468 {ISD::SMIN, MVT::v4i8, 5}, // pminsb
5469 {ISD::SMIN, MVT::v8i8, 7}, // pminsb
5470 {ISD::SMIN, MVT::v16i8, 6},
5471 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2
5472 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2
5473 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2
5474 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax
5478 {ISD::SMIN, MVT::v16i16, 6},
5479 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax
5480 {ISD::SMIN, MVT::v32i8, 8},
5481 {ISD::UMIN, MVT::v32i8, 8},
5485 {ISD::SMIN, MVT::v32i16, 8},
5486 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax
5487 {ISD::SMIN, MVT::v64i8, 10},
5488 {ISD::UMIN, MVT::v64i8, 10},
5498 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
5502 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5506 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
5510 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5530 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
5534 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5538 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
5542 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
6116 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);