Lines Matching defs:isKill

1162                                   bool &isKill, MachineOperand &ImplicitOp,
1172 isKill = MI.killsRegister(SrcReg, /*TRI=*/nullptr);
1202 .addReg(SrcReg, getKillRegState(isKill));
1205 isKill = true;
1264 bool IsKill = MI.getOperand(1).isKill();
1310 bool IsKill2 = MI.getOperand(2).isKill();
1469 bool isKill;
1471 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1479 .addReg(SrcReg, getKillRegState(isKill))
1507 bool isKill;
1509 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1515 .addReg(SrcReg, getKillRegState(isKill));
1533 bool isKill;
1535 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1541 .addReg(SrcReg, getKillRegState(isKill));
1577 bool isKill;
1582 isKill = isKill2;
1585 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1596 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1627 bool isKill;
1629 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1635 .addReg(SrcReg, getKillRegState(isKill));
1667 bool isKill;
1669 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1675 .addReg(SrcReg, getKillRegState(isKill));
2027 if (Op.isReg() && (Op.isDead() || Op.isKill()))
4686 bool isKill) const {
4698 .addReg(Reg, getKillRegState(isKill));
4722 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
4736 loadStoreTileReg(MBB, MI, Opc, SrcReg, FrameIdx, isKill);
4739 .addReg(SrcReg, getKillRegState(isKill));
5766 /*isKill=*/false,
8417 // Address operands cannot be marked isKill.
8441 getKillRegState(ImpOp.isKill()) |
10477 if (MI.isDebugInstr() || MI.isKill())
10791 bool IsKill = Root.getOperand(1).isKill();