Lines Matching defs:NewMI

1006   MachineInstr &NewMI = *std::prev(I);
1007   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1336   MachineInstr *NewMI = MIB;
1344     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1346       LV->getVarInfo(InRegLEA2).Kills.push_back(NewMI);
1362     SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1430   MachineInstr *NewMI = nullptr;
1451     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1484     NewMI = MIB;
1488       LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1519     NewMI = addOffset(MIB, 1);
1523       LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1545     NewMI = addOffset(MIB, -1);
1549       LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1596     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1601         LV->getVarInfo(SrcReg2).Kills.push_back(NewMI);
1603         LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1618     NewMI = addOffset(
1639     NewMI = addOffset(MIB, MI.getOperand(2));
1643       LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1679     NewMI = addOffset(MIB, -Imm);
1683       LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1698     NewMI = addOffset(MIB, -Imm);
1872     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2011     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2021   if (!NewMI)
2028         LV->replaceKillInstruction(Op.getReg(), MI, *NewMI);
2033   MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
2036     LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
2043   return NewMI;
2283 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2287     return std::exchange(NewMI, false)
2710   return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
4696     MachineInstr *NewMI =
4699     MachineOperand &MO = NewMI->getOperand(X86::AddrIndexReg);
4710     MachineInstr *NewMI = addFrameReference(
4712     MachineOperand &MO = NewMI->getOperand(1 + X86::AddrIndexReg);
6229     MachineInstr *NewMI = BuildMI(MBB, MI, MIB->getDebugLoc(),
6237     assert(NewMI->getOperand(2).getReg() == X86::EFLAGS &&
6239     NewMI->getOperand(2).setIsUndef();
6240     assert(NewMI->getOperand(3).getReg() == X86::DF &&
6242     NewMI->getOperand(3).setIsUndef();
7120                                         MachineInstr &NewMI,
7125   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
7126     MachineOperand &MO = NewMI.getOperand(Idx);
7135         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
7140           NewMI.dump(); dbgs() << "\n");
7152   MachineInstr *NewMI =
7154   MachineInstrBuilder MIB(MF, NewMI);
7166   updateOperandRegConstraints(MF, *NewMI, TII);
7169   MBB->insert(InsertPt, NewMI);
7180   MachineInstr *NewMI =
7182   MachineInstrBuilder MIB(MF, NewMI);
7194   updateOperandRegConstraints(MF, *NewMI, TII);
7198     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
7201   MBB->insert(InsertPt, NewMI);
7243         MachineInstr *NewMI =
7245         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
7246         return NewMI;
7265         MachineInstr *NewMI =
7267         return NewMI;
7280         MachineInstr *NewMI =
7282         return NewMI;
7287     if (auto *NewMI =
7290       return NewMI;
7402   MachineInstr *NewMI = nullptr;
7434     NewMI = IsTwoAddr ? fuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this)
7441       Register DstReg = NewMI->getOperand(0).getReg();
7443         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
7445         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
7447     return NewMI;
7459     NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
7461     if (NewMI)
7462       return NewMI;
8257     MachineInstr *NewMI =
8260     if (NewMI)
8261       return NewMI;