Lines Matching defs:Ins
1095 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1104 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1294 const SmallVectorImpl<ISD::InputArg> &Ins,
1299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1333 EVT ArgVT = Ins[i].ArgVT;
1348 if (Ins[i].PartOffset == 0) {
1377 DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
1380 DAG.getMachineFunction(), FI, Ins[i].PartOffset));
1672 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1698 CCInfo.AnalyzeArguments(Ins, CC_X86);
1703 CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
1714 assert(InsIndex < Ins.size() && "Invalid Ins index");
1801 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
1806 !(Ins[I].Flags.isByVal() && VA.isRegLoc())) {
1814 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
1815 if (Ins[I].Flags.isSwiftAsync()) {
1841 if (Ins[I].Flags.isSRet()) {
1868 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
1875 if (!canGuaranteeTCO(CallConv) && hasCalleePopSRet(Ins, Subtarget))
1911 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
1912 if (Ins[I].Flags.isSwiftSelf() || Ins[I].Flags.isSwiftAsync() ||
1913 Ins[I].Flags.isSwiftError()) {
1998 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2582 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl, DAG,
2736 const SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2813 for (const auto &In : Ins) {
2822 RVCCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2830 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,