Lines Matching defs:ArgLocs

1455 static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
1457       ArgLocs, [](const CCValAssign &A, const CCValAssign &B) -> bool {
1691   SmallVector<CCValAssign, 16> ArgLocs;
1692   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1708   assert(isSortedByValueNo(ArgLocs) &&
1712   for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
1715     CCValAssign &VA = ArgLocs[I];
1727             getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget);
2027   SmallVector<CCValAssign, 16> ArgLocs;
2028   CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2057     isTailCall = IsEligibleForTailCallOptimization(CLI, CCInfo, ArgLocs,
2108     if (!ArgLocs.back().isMemLoc())
2111     if (ArgLocs.back().getLocMemOffset() != 0)
2115     assert(ArgLocs.back().isMemLoc() &&
2121         PreallocatedOffsets.push_back(ArgLocs[i].getLocMemOffset());
2147   assert(isSortedByValueNo(ArgLocs) &&
2153   for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
2161     CCValAssign &VA = ArgLocs[I];
2223       Passv64i1ArgInRegs(dl, DAG, Arg, RegsToPass, VA, ArgLocs[++I], Subtarget);
2331     for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
2333       CCValAssign &VA = ArgLocs[I];
2732     SmallVectorImpl<CCValAssign> &ArgLocs, bool IsCalleePopSRet) const {
2804     for (const auto &VA : ArgLocs)
2853       for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
2854         const CCValAssign &VA = ArgLocs[I];
2881       for (const auto &VA : ArgLocs) {
2896     if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))