Lines Matching +full:vrange +full:- +full:high +full:- +full:enable
1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
62 /// #0 - The incoming token chain
63 /// #1 - The callee
64 /// #2 - The number of arg bytes the caller pushes on the stack.
65 /// #3 - The number of arg bytes the callee pops off the stack.
66 /// #4 - The value to pass in AL/AX/EAX (optional)
67 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// #0 - The outgoing token chain
72 /// #1 - The first register result value (optional)
73 /// #2 - The second register result value (optional)
90 /// X86 bit-test instructions.
151 /// Special wrapper used under X86-64 PIC mode for RIP
155 /// Copies a 64-bit value from an MMX vector to the low word
156 /// of an XMM vector, with the high word zero filled.
159 /// Copies a 64-bit value from the low word of an XMM vector
163 /// Copies a 32-bit value from the low word of a MMX
167 /// Copies a GPR into the low 32-bit word of a MMX vector
168 /// and zero out the high word.
171 /// Extract an 8-bit value from a vector and zero extend it to
175 /// Extract a 16-bit value from a vector and zero extend it to
183 /// Insert the lower 8-bits of a 32-bit value to a vector,
187 /// Insert the lower 16-bits of a 32-bit value to a vector,
191 /// Shuffle 16 8-bit values within a vector.
196 /// Compute Double Block Packed Sum-Absolute-Differences
205 /// Dynamic (non-constant condition) vector blend where only the sign bits
275 /// Floating point reciprocal-sqrt and reciprocal approximation.
281 // AVX-512 reciprocal approximations with a little more precision.
327 // Masked version of the above. Used when less than a 128-bit result is
347 // Masked version of above. Used for v2f64->v4f32.
351 // 128-bit vector logical left / right shift
413 // Zero High Bits Starting with Specified Bit Position.
420 // X86-specific multiply by immediate.
443 // Intra-lane alignr.
445 // AVX512 inter-lane alignr.
456 // Shuffle Packed Values at 128-bit granularity.
477 // 3-op Variable Permute (VPERMT2).
489 VRANGE,
493 // Reduce - Perform Reduction Transformation on scalar\packed FP.
498 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
555 // We use the target independent ISD::FMA for the non-inverted case.
570 // AVX512-FP16 complex addition and multiplication.
605 // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
639 // Masked versions of above. Used for v2f64->v4f32.
679 // Get a NIST SP800-90B & C compliant random integer and
684 // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
685 // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
702 // Conversions between float and half-float.
729 // For avx512-vp2intersect
732 // User level interrupts - testui
763 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
777 // Conversions between float and half-float.
784 // WARNING: Only add nodes here if they are strict FP nodes. Non-memory and
785 // non-strict FP nodes should be above FIRST_TARGET_STRICTFP_OPCODE.
793 /// LOCK-prefixed arithmetic read-modify-write instructions.
852 /// This instruction implements a fp->int store from FP stack
976 //===--------------------------------------------------------------------===//
1007 /// that contains are placed at 16-byte boundaries while the rest are at
1008 /// 4-byte boundaries.
1103 /// with x86-specific store splitting optimizations.
1119 // save two bitwise instructions and one float-to-int instruction and
1121 // significant benefit because it avoids the float->int domain switch
1169 auto VTIsOk = [](EVT VT) -> bool {
1196 /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
1338 /// This is used to enable splatted operand transforms for vector shifts
1342 /// Add x86-specific opcodes to the default list.
1350 /// register EAX to i16 by referencing its sub-register AX.
1357 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1361 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1362 /// all instructions that define 32-bit values implicit zero-extend the
1514 /// some non-standard address space, and populates the address space and
1721 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
1722 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1763 // Utility function to emit the low-level va_arg code for X86-64.
1862 return N->getOpcode() == X86ISD::MGATHER ||
1863 N->getOpcode() == X86ISD::MSCATTER;
1872 return N->getOpcode() == X86ISD::MGATHER;
1881 return N->getOpcode() == X86ISD::MSCATTER;
1889 /// Similar to unpacklo/unpackhi, but without the 128-bit lane limitation
1891 /// v8iX Lo --> <0, 0, 1, 1, 2, 2, 3, 3>
1892 /// v8iX Hi --> <4, 4, 5, 5, 6, 6, 7, 7>