Lines Matching defs:SubVec
4330 SDValue SubVec = Op.getOperand(1);
4335 if (SubVec.isUndef())
4354 SubVec, Idx);
4358 MVT SubVecVT = SubVec.getSimpleValueType();
4373 // Merge them together, SubVec should be zero extended.
4374 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
4376 SubVec, ZeroIdx);
4377 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
4381 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
4382 Undef, SubVec, ZeroIdx);
4386 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4388 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
4396 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4402 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4405 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
4408 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
4413 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4431 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
4452 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4454 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
4456 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
4463 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4465 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
4484 SubVec = DAG.getNode(ISD::OR, dl, WideOpVT, SubVec, Vec);
4487 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
9228 SDValue SubVec = Op.getOperand(i);
9229 if (SubVec.isUndef())
9231 if (ISD::isFreezeUndef(SubVec.getNode())) {
9233 if (SubVec.hasOneUse())
9238 else if (ISD::isBuildVectorAllZeros(SubVec.getNode()))
9294 SDValue SubVec = Op.getOperand(i);
9295 if (SubVec.isUndef())
9298 if (ISD::isBuildVectorAllZeros(SubVec.getNode()))
9312 SDValue SubVec = Op.getOperand(Idx);
9313 unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements();
9315 Op = widenSubVector(ShiftVT, SubVec, false, Subtarget, DAG, dl);
9328 SDValue SubVec = Op.getOperand(Idx);
9329 unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements();
9330 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec,
15004 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
15007 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec,
16676 SDValue SubVec =
16679 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec,
49607 SDValue SubVec = Src.getOperand(0);
49608 EVT SubVecVT = SubVec.getValueType();
49610 // The RHS of the AND should be a mask with as many bits as SubVec.
49628 if (!(IsLegalSetCC(SubVec) || (SubVec.getOpcode() == ISD::AND &&
49629 (IsLegalSetCC(SubVec.getOperand(0)) ||
49630 IsLegalSetCC(SubVec.getOperand(1))))))
49638 Ops[0] = SubVec;
56788 SDValue SubVec = N->getOperand(1);
56791 MVT SubVecVT = SubVec.getSimpleValueType();
56793 if (Vec.isUndef() && SubVec.isUndef())
56798 (SubVec.isUndef() || ISD::isBuildVectorAllZeros(SubVec.getNode())))
56804 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR &&
56805 ISD::isBuildVectorAllZeros(SubVec.getOperand(0).getNode())) {
56806 uint64_t Idx2Val = SubVec.getConstantOperandVal(2);
56809 SubVec.getOperand(1),
56817 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 &&
56818 isNullConstant(SubVec.getOperand(1)) &&
56819 SubVec.getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR) {
56820 SDValue Ins = SubVec.getOperand(0);
56840 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR &&
56841 SubVec.getOperand(0).isUndef() && isNullConstant(SubVec.getOperand(2)))
56843 SubVec.getOperand(1), N->getOperand(2));
56847 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
56848 SubVec.getOperand(0).getSimpleValueType() == OpVT &&
56851 int ExtIdxVal = SubVec.getConstantOperandVal(1);
56863 return DAG.getVectorShuffle(OpVT, dl, Vec, SubVec.getOperand(0), Mask);
56896 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST)
56897 return DAG.getNode(X86ISD::VBROADCAST, dl, OpVT, SubVec.getOperand(0));
56901 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() &&
56902 SubVec.getOpcode() == X86ISD::VBROADCAST_LOAD) {
56903 auto *MemIntr = cast<MemIntrinsicSDNode>(SubVec);
56916 if (IdxVal == (OpVT.getVectorNumElements() / 2) && SubVec.hasOneUse() &&
56917 Vec.getValueSizeInBits() == (2 * SubVec.getValueSizeInBits())) {
56919 auto *SubLd = dyn_cast<LoadSDNode>(SubVec);
56922 SubVec.getValueSizeInBits() / 8, 0))