Lines Matching defs:Shuffle
5739 KnownZero.getBitWidth() == NumElts && "Shuffle mask size mismatch");
6434 assert(0 <= Elt && Elt < (2 * NumElems) && "Shuffle index out of range");
9803 // The Shuffle result is as follow:
10572 assert(Mask.size() <= 64 && "Shuffle mask too big for blend mask");
10820 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
10976 // Shuffle the inputs into place.
11163 // Shuffle the input elements into the desired positions in V1 and V2 and
11601 // by performing 3 byte shifts. Shuffle combining can kick in above that.
13317 assert(Mask.size() == 8 && "Shuffle mask length doesn't match!");
14620 assert((!SimpleOnly || (!UseHiV1 && !UseHiV2)) && "Shuffle isn't simple");
15473 // Shuffle the (lowest) repeated elements in place for broadcast.
15476 // Shuffle the actual broadcast.
15591 // Shuffle each source sub-lane to its destination.
15628 if (SDValue Shuffle = ShuffleSubLanes(Scale))
15629 return Shuffle;
16656 assert(Widened128Mask.size() == 4 && "Shuffle widening mismatch");
17278 // Shuffle should be unary.
17476 SDValue Shuffle = DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask);
17482 Shuffle, ISD::SETGT);
17484 return DAG.getNode(ISD::TRUNCATE, DL, VT, Shuffle);
17681 // Shuffle mask widening should not interfere with a broadcast opportunity
18148 // Shuffle the element to the lowest element, then movss or movsh.
19547 SDValue Shuffle = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, Sub, {1,-1});
19548 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuffle, Sub);
28765 // Shuffle it back into the right order.
37606 "Shuffle index out of range");
37772 "Shuffle index out of range");
37826 const X86Subtarget &Subtarget, unsigned &Shuffle,
37837 Shuffle = X86ISD::VZEXT_MOVL;
37878 Shuffle = unsigned(
37882 Shuffle = DAG.getOpcode_EXTEND_VECTOR_INREG(Shuffle);
37896 Shuffle = X86ISD::VZEXT_MOVL;
37909 Shuffle = X86ISD::MOVDDUP;
37914 Shuffle = X86ISD::MOVSLDUP;
37919 Shuffle = X86ISD::MOVSHDUP;
37928 Shuffle = X86ISD::MOVDDUP;
37934 Shuffle = X86ISD::MOVSLDUP;
37940 Shuffle = X86ISD::MOVSHDUP;
37951 Shuffle = X86ISD::MOVDDUP;
37958 Shuffle = X86ISD::MOVSLDUP;
37965 Shuffle = X86ISD::MOVSHDUP;
37982 unsigned &Shuffle, MVT &ShuffleVT,
37996 Shuffle = X86ISD::VPERMI;
38004 Shuffle = X86ISD::VPERMI;
38012 Shuffle = X86ISD::VPERMILPI;
38042 Shuffle = (AllowIntDomain ? X86ISD::PSHUFD : X86ISD::VPERMILPI);
38063 Shuffle = X86ISD::PSHUFLW;
38077 Shuffle = X86ISD::PSHUFHW;
38092 Shuffle = X86ISD::VROTLI;
38104 matchShuffleAsShift(ShuffleVT, Shuffle, MaskScalarSizeInBits, Mask, 0,
38110 (Shuffle == X86ISD::VSHLDQ || Shuffle == X86ISD::VSRLDQ))
38130 unsigned &Shuffle, MVT &SrcVT, MVT &DstVT,
38141 Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKL : X86ISD::MOVLHPS;
38148 Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKH : X86ISD::MOVHLPS;
38155 Shuffle = X86ISD::MOVSD;
38161 Shuffle = X86ISD::MOVSS;
38168 Shuffle = X86ISD::MOVSH;
38178 if (matchShuffleWithPACK(MaskVT, SrcVT, V1, V2, Shuffle, Mask, DAG,
38195 Shuffle = X86ISD::PACKUS;
38202 Shuffle = X86ISD::PACKUS;
38209 Shuffle = X86ISD::PACKSS;
38221 if (matchShuffleWithUNPCK(MaskVT, V1, V2, Shuffle, IsUnary, Mask, DL, DAG,
38267 Shuffle = ISD::OR;
38311 Shuffle = ISD::OR;
38326 unsigned &Shuffle, MVT &ShuffleVT, unsigned &PermuteImm) {
38338 Shuffle = X86ISD::VALIGN;
38355 Shuffle = X86ISD::PALIGNR;
38384 Shuffle = X86ISD::BLENDI;
38392 Shuffle = X86ISD::BLENDI;
38404 Shuffle = X86ISD::INSERTPS;
38419 Shuffle = X86ISD::SHUFP;
38464 Shuffle = X86ISD::SHUFP;
38476 Shuffle = X86ISD::INSERTPS;
38764 unsigned Shuffle, PermuteImm;
38805 DAG, Subtarget, Shuffle, ShuffleSrcVT, ShuffleVT) &&
38808 if (Depth == 0 && Root.getOpcode() == Shuffle)
38811 Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res);
38816 AllowIntDomain, DAG, Subtarget, Shuffle, ShuffleVT,
38820 if (Depth == 0 && Root.getOpcode() == Shuffle)
38823 Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res,
38867 NewV2, DL, DAG, Subtarget, Shuffle, ShuffleSrcVT,
38870 if (Depth == 0 && Root.getOpcode() == Shuffle)
38874 Res = DAG.getNode(Shuffle, DL, ShuffleVT, NewV1, NewV2);
38882 Subtarget, Shuffle, ShuffleVT, PermuteImm) &&
38884 if (Depth == 0 && Root.getOpcode() == Shuffle)
38888 Res = DAG.getNode(Shuffle, DL, ShuffleVT, NewV1, NewV2,
39113 // Bits[2:1] - (Per Lane) PD Shuffle Mask.
39114 // Bits[2:0] - (Per Lane) PS Shuffle Mask.
39315 assert(!WideInputs.empty() && "Shuffle with no inputs detected");
39605 // Shuffle the constant bits according to the mask.
39761 // Shuffle inputs must not be larger than the shuffle result.
39972 assert(!Ops.empty() && "Shuffle with no inputs detected");
40112 if (SDValue Shuffle = combineX86ShuffleChain(
40115 return Shuffle;
41316 assert(0 <= M && M < 8 && "Shuffle index out of range");
41785 if (SDValue Shuffle = combineTargetShuffle(Op, dl, DAG, DCI, Subtarget))
41786 return Shuffle;
42570 // Shuffle inputs must be the same size as the result.
43302 "Shuffle mask index out of range");
44548 SDValue Shuffle =
44550 DP = DAG.getNode(ISD::ADD, DL, DpVT, DP, Shuffle);
44622 SDValue Shuffle =
44624 SAD = DAG.getNode(ISD::ADD, DL, SadVT, SAD, Shuffle);
44814 // Shuffle inputs must be the same size as the result.
50100 if (SDValue Shuffle = combineX86ShufflesRecursively(
50105 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Shuffle,
52075 // Shuffle folding should merge these back together.