Lines Matching defs:ShiftVT

9314     MVT ShiftVT = widenMaskVectorType(ResVT, Subtarget);
9315     Op = widenSubVector(ShiftVT, SubVec, false, Subtarget, DAG, dl);
9316     Op = DAG.getNode(X86ISD::KSHIFTL, dl, ShiftVT, Op,
11640 static int matchShuffleAsShift(MVT &ShiftVT, unsigned &Opcode,
11677     ShiftVT = ByteShift ? MVT::getVectorVT(MVT::i8, SizeInBits / 8)
11710   MVT ShiftVT;
11715   int ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(),
11720     ShiftAmt = matchShuffleAsShift(ShiftVT, Opcode, VT.getScalarSizeInBits(),
11731   assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
11733   V = DAG.getBitcast(ShiftVT, V);
11734   V = DAG.getNode(Opcode, DL, ShiftVT, V,
29277     MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
29313       SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT, R,
29322       SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT, R,
47976     EVT ShiftVT = VT.isVector() ? VT : MVT::i8;
47986                       DAG.getConstant(Log2_64(AbsMulAmt - 1), DL, ShiftVT)));
47993                       DAG.getConstant(Log2_64(AbsMulAmt + 1), DL, ShiftVT));
48004                       DAG.getConstant(Log2_64(AbsMulAmt - 2), DL, ShiftVT));
48013                       DAG.getConstant(Log2_64(AbsMulAmt + 2), DL, ShiftVT));
48033                         DAG.getConstant(Log2_64(ShiftAmt1), DL, ShiftVT));
48036                         DAG.getConstant(Log2_64(AbsMulAmtLowBit), DL, ShiftVT));
54559       MVT ShiftVT = SrcVT;
54562       if (ShiftVT.getScalarType() == MVT::i8) {
54564         ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
54565         ShiftLHS = DAG.getBitcast(ShiftVT, ShiftLHS);
54566         ShiftRHS = DAG.getBitcast(ShiftVT, ShiftRHS);
54568       ShiftLHS = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, ShiftVT,
54570       ShiftRHS = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, ShiftVT,