Lines Matching defs:SetCC
23849 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
24011 SDValue SetCC = getSETCC(Cond, Overflow, DL, DAG);
24013 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC);
25943 SDValue SetCC;
25946 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG);
25948 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP);
25952 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG);
25954 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP);
25959 SetCC = getSETCC(X86::COND_A, Comi, dl, DAG);
25964 SetCC = getSETCC(X86::COND_AE, Comi, dl, DAG);
25969 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
26095 SDValue SetCC = getSETCC(X86::COND_B, Res.getValue(1), dl, DAG);
26096 SDValue Results[] = { SetCC, Res };
26252 SDValue SetCC = getSETCC(X86CC, Test, dl, DAG);
26253 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
26314 SDValue SetCC = getSETCC(X86CC, PCMP, dl, DAG);
26315 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
26882 SDValue SetCC = getSETCC(X86::COND_B, Operation.getValue(0), dl, DAG);
26883 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
26903 SDValue SetCC = getSETCC(X86::COND_E, Operation.getValue(0), dl, DAG);
26904 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
26993 SDValue SetCC = getSETCC(X86::COND_B, Operation.getValue(0), dl, DAG);
26994 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
27228 SDValue SetCC = getSETCC(X86::COND_NE, InTrans, dl, DAG);
27229 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
31844 SDValue SetCC = getSETCC(IsSigned ? X86::COND_O : X86::COND_B,
31847 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
31849 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
46610 // an SetCC or extended from it.
46614 SDValue SetCC;
46620 SetCC = Op2;
46622 SetCC = Op1;
46635 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
46636 SetCC.getOpcode() == ISD::TRUNCATE ||
46637 SetCC.getOpcode() == ISD::AND) {
46638 if (SetCC.getOpcode() == ISD::AND) {
46640 if (isOneConstant(SetCC.getOperand(0)))
46642 if (isOneConstant(SetCC.getOperand(1)))
46646 SetCC = SetCC.getOperand(OpIdx);
46649 SetCC = SetCC.getOperand(0);
46652 switch (SetCC.getOpcode()) {
46660 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
46665 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
46668 return SetCC.getOperand(1);
46671 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
46672 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
46678 SDValue Op = SetCC.getOperand(0);
46703 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
46706 return SetCC.getOperand(3);
49727 SDValue SetCC = N->getOperand(0);
49729 if (SetCC.getOpcode() != X86ISD::SETCC || !Flag.hasOneUse())
49741 SDValue X = SetCC.getOperand(1);
49747 SDValue CCN = SetCC.getOperand(0);
49934 if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget))
49935 return SetCC;
50722 if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget))
50723 return SetCC;
50749 // (0 - SetCC) | C -> (zext (not SetCC)) * (C + 1) - 1 if we can get a LEA out of it.
50862 // SetCC on x86 zero extends so only act on this if it's a logical shift.
53078 if (SDValue SetCC = foldXor1SetCC(N, DAG))
53079 return SetCC;
55898 SDValue SetCC = Op1.getOperand(0);
55899 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
55903 SDValue NewSetCC = getSETCC(NewCC, SetCC.getOperand(1), DL, DAG);
55924 SDValue SetCC = Sub.getOperand(1);
55926 if (!X86::isZeroNode(Sub.getOperand(0)) || SetCC.getOpcode() != X86ISD::SETCC)
55930 Ops[3] = SetCC.getOperand(0);
55931 Ops[4] = SetCC.getOperand(1);