Lines Matching defs:SRL
1288 setOperationAction(ISD::SRL, VT, Custom);
1493 setOperationAction(ISD::SRL, VT, Custom);
1922 setOperationAction(ISD::SRL, VT, Custom);
2519 ISD::SRL,
3387 if (ShiftOpc == ISD::SHL || ShiftOpc == ISD::SRL) {
3404 return AndMask->getSignificantBits() > 32 ? (unsigned)ISD::SRL
3410 return ShiftOrRotateAmt.uge(7) ? (unsigned)ISD::SRL : ShiftOpc;
3422 // We prefer rotate for vectors of if we won't get a zext mask with SRL
3427 // Non-vector type and we have a zext mask with SRL.
3428 return ISD::SRL;
3459 N->getOperand(0).getOpcode() == ISD::SRL) ||
3460 (N->getOpcode() == ISD::SRL &&
6864 case ISD::SRL:
8377 case ISD::SRL:
11312 // expanded to OR(SRL,SHL), will be more efficient, but if they can
11323 SDValue SRL = DAG.getNode(X86ISD::VSRLI, DL, RotateVT, V1,
11325 SDValue Rot = DAG.getNode(ISD::OR, DL, RotateVT, SHL, SRL);
12384 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
17586 case ISD::SRL:
18126 Res = DAG.getNode(ISD::SRL, dl, MVT::i32, Res,
18138 Res = DAG.getNode(ISD::SRL, dl, MVT::i16, Res,
19260 DAG.getNode(ISD::SRL, DL, MVT::v4i64, Src, One),
19762 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
20238 return DAG.getNode(ISD::SRL, DL, VT, Extend,
20441 /// possibly by converting a SRL node to SRA for sign extension.
20518 if (In.getOpcode() == ISD::SRL && In->hasOneUse())
23004 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
25167 case ISD::SRL:
25216 ShiftOpc = ISD::SRL;
27667 DAG.getNode(ISD::SRL, DL, MVT::i16,
27676 DAG.getNode(ISD::SRL, DL, MVT::i32, LUT, Shift),
27979 SDValue Hi = DAG.getNode(ISD::SRL, DL, CurrVT, Op0, NibbleShift);
28022 SDValue R0 = DAG.getNode(ISD::SRL, DL, NextVT, ResNext, Shift);
28023 SDValue R1 = DAG.getNode(ISD::SRL, DL, NextVT, HiZ, Shift);
29090 case ISD::SRL:
29094 return (getGFNICtrlImm(ISD::SRL, Amt) |
29097 return getGFNICtrlImm(ISD::SRL, 8 - Amt) | getGFNICtrlImm(ISD::SHL, Amt);
29099 return getGFNICtrlImm(ISD::SHL, 8 - Amt) | getGFNICtrlImm(ISD::SRL, Amt);
29122 assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
29158 assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
29216 // SRA upper i32, SRL whole i64 and select lower i32.
29267 if ((Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL) &&
29320 if (Op.getOpcode() == ISD::SRL) {
29322 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT, R,
29324 SRL = DAG.getBitcast(VT, SRL);
29327 return DAG.getNode(ISD::AND, dl, VT, SRL, DAG.getConstant(Mask, dl, VT));
29331 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
29367 unsigned LogicalOp = (Opcode == ISD::SHL ? ISD::SHL : ISD::SRL);
29495 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
29496 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
29506 if (Opc == ISD::SRL || Opc == ISD::SRA)
29508 if (Opc == ISD::SHL || Opc == ISD::SRL)
29586 // Constant ISD::SRL can be performed efficiently on vXi16 vectors as we
29588 if (Opc == ISD::SRL && ConstantAmt &&
29698 // Constant ISD::SRA/SRL can be performed efficiently on vXi8 vectors as we
29700 if (ConstantAmt && (Opc == ISD::SRA || Opc == ISD::SRL) &&
29788 if (Opc == ISD::SHL || Opc == ISD::SRL) {
30009 DAG.getNode(ISD::SRL, DL, WideVT, DAG.getBitcast(WideVT, Op1),
30020 SDValue ShY = DAG.getNode(ISD::SRL, DL, VT, Op1,
30033 unsigned ShiftOpc = IsFSHR ? ISD::SRL : ISD::SHL;
30128 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, Res, Amt);
30131 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, Res, HiShift);
30247 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, R,
30291 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL;
30361 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL;
30362 unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL;
30402 supportedVectorVarShift(VT, Subtarget, ISD::SRL);
30410 SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt);
30411 SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR);
30412 return DAG.getNode(ISD::OR, DL, VT, SHL, SRL);
31269 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), ShifterV);
31304 SDValue HiNibbles = DAG.getNode(ISD::SRL, DL, VT, Op, FourV);
31383 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
31387 DAG.getNode(ISD::SRL, DL, MVT::i32, Op,
31395 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
31400 Op = DAG.getNode(ISD::SRL, DL, MVT::i32,
31412 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
31417 Op = DAG.getNode(ISD::SRL, DL, MVT::i64, LUT,
31428 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
31433 Op = DAG.getNode(ISD::SRL, DL, MVT::i32, Op,
31437 Op = DAG.getNode(ISD::SRL, DL, MVT::i32, Op,
31556 SDValue Hi = DAG.getNode(ISD::SRL, DL, VT, In, DAG.getConstant(4, DL, VT));
31607 DAG.getNode(ISD::SRL, DL, MVT::i64, X,
31615 SDValue Hi16 = DAG.getNode(ISD::SRL, DL, MVT::i32, X,
31627 DAG.getNode(ISD::SRL, DL, MVT::i32, X, DAG.getConstant(8, DL, MVT::i8)));
32463 case ISD::SRL:
32561 SDValue Op = DAG.getNode(ISD::SRL, dl, MVT::i64, N->getOperand(0),
32616 // TODO: Could use SRL+TRUNCATE but that doesn't become a PSHUFD.
33192 DAG.getNode(ISD::SRL, dl, SrcVT, Src, One),
40872 if (TruncIn.getOpcode() == ISD::SRL &&
44756 Scl = DAG.getNode(ISD::SRL, dl, SclVT, Scl,
45450 return DAG.getNode(ISD::SRL, DL, VT, Vec,
46257 // Unlike general shift instructions (SHL/SRL), AVX2's VSHLV/VSRLV handle
46266 if ((LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SHL) &&
46272 return DAG.getNode(LHS.getOpcode() == ISD::SRL ? X86ISD::VSRLV
46278 if ((RHS.getOpcode() == ISD::SRL || RHS.getOpcode() == ISD::SHL) &&
46284 return DAG.getNode(RHS.getOpcode() == ISD::SRL ? X86ISD::VSRLV
46803 if (Carry.getOpcode() == ISD::SRL) {
48055 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
48056 "SRL or SRA node is required here!");
48253 supportedVectorVarShift(VT, Subtarget, ISD::SRL)) {
48307 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
49434 if (!supportedVectorShiftWithImm(VT, Subtarget, ISD::SRL))
49550 SDValue LShr = DAG.getNode(ISD::SRL, dl, VT, AllOnes, Sub);
49984 // Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y), COND_B) iff Y is not a constant
49994 // Peek through AND(NOT(SRL(X,Y)),1).
50000 if (Src.getOpcode() == ISD::SRL &&
50004 // Peek through AND(SRL(NOT(X),Y),1).
50285 SDValue Scc = DAG.getNode(ISD::SRL, dl, MVT::i32, Trunc,
50428 /// Also try (ADD/SUB)+(AND(SRL,1)) bit extraction pattern with BT+{ADC, SBB}.
50842 /// XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
50864 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
52401 if (Src.getOpcode() != ISD::SRL ||
55171 if ((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) &&
55178 APInt Mask = Op.getOpcode() == ISD::SRL
56419 // Special case: SHL/SRL AVX1 V4i64 by 32-bits can lower as a shuffle.
57780 case ISD::SRL: return combineShiftRightLogical(N, DAG, DCI, Subtarget);
57984 case ISD::SRL:
58087 case ISD::SRL: {