Lines Matching defs:SHL
1289 setOperationAction(ISD::SHL, VT, Custom);
1494 setOperationAction(ISD::SHL, VT, Custom);
1923 setOperationAction(ISD::SHL, VT, Custom);
2517 ISD::SHL,
3361 return NewShiftOpcode == ISD::SHL;
3387 if (ShiftOpc == ISD::SHL || ShiftOpc == ISD::SRL) {
3400 if (ShiftOpc == ISD::SHL) {
3416 return AndMask->getSignificantBits() > 33 ? (unsigned)ISD::SHL : ShiftOpc;
3419 return ShiftOrRotateAmt.ult(7) ? (unsigned)ISD::SHL : ShiftOpc;
3458 assert(((N->getOpcode() == ISD::SHL &&
3461 N->getOperand(0).getOpcode() == ISD::SHL)) &&
6564 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt,
6593 NextElt = DAG.getNode(ISD::SHL, DL, MVT::i32, NextElt,
8376 case ISD::SHL:
11312 // expanded to OR(SRL,SHL), will be more efficient, but if they can
11321 SDValue SHL = DAG.getNode(X86ISD::VSHLI, DL, RotateVT, V1,
11325 SDValue Rot = DAG.getNode(ISD::OR, DL, RotateVT, SHL, SRL);
17585 case ISD::SHL:
18963 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
20101 Adjust = DAG.getNode(ISD::SHL, DL, MVT::i64, Zext, Const63);
20634 In = DAG.getNode(ISD::SHL, DL, ExtVT,
20687 In = DAG.getNode(ISD::SHL, DL, InVT, In,
22618 case ISD::SHL:
22983 if (Op1.getOpcode() == ISD::SHL)
22985 if (Op0.getOpcode() == ISD::SHL) {
23462 // ICMP_EQ(AND(X,C),C) -> SRA(SHL(X,LOG2(C)),BW-1) iff C is power-of-2.
23471 Result = DAG.getNode(ISD::SHL, dl, VT, Result,
25163 case ISD::SHL:
25213 ShiftOpc = ISD::SHL;
26663 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
27036 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
27743 DAG.getNode(ISD::SHL, DL, MVT::i32, NewRM,
27747 DAG.getNode(ISD::SHL, DL, MVT::i16, DAG.getConstant(0xc9, DL, MVT::i16),
27781 RMBits = DAG.getNode(ISD::SHL, DL, MVT::i32, RMBits,
28671 LoOp = DAG.getNode(ISD::SHL, dl, MVT::i16, LoOp,
28673 HiOp = DAG.getNode(ISD::SHL, dl, MVT::i16, HiOp,
29087 case ISD::SHL:
29097 return getGFNICtrlImm(ISD::SRL, 8 - Amt) | getGFNICtrlImm(ISD::SHL, Amt);
29099 return getGFNICtrlImm(ISD::SHL, 8 - Amt) | getGFNICtrlImm(ISD::SRL, Amt);
29122 assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
29158 assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
29246 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1) {
29267 if ((Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL) &&
29280 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1) {
29311 if (Op.getOpcode() == ISD::SHL) {
29313 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT, R,
29315 SHL = DAG.getBitcast(VT, SHL);
29318 return DAG.getNode(ISD::AND, dl, VT, SHL, DAG.getConstant(Mask, dl, VT));
29367 unsigned LogicalOp = (Opcode == ISD::SHL ? ISD::SHL : ISD::SRL);
29375 if (Opcode != ISD::SHL)
29441 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
29508 if (Opc == ISD::SHL || Opc == ISD::SRL)
29563 (VT == MVT::v4i32 || Subtarget.hasSSE41() || Opc != ISD::SHL ||
29581 if (Opc == ISD::SHL && !(VT == MVT::v32i8 && (Subtarget.hasXOP() ||
29712 Amt = DAG.getNode(ISD::SHL, dl, ExVT, DAG.getConstant(1, dl, ExVT), Amt);
29788 if (Opc == ISD::SHL || Opc == ISD::SRL) {
29999 supportedVectorShiftWithImm(WideVT, Subtarget, ISD::SHL)))) {
30006 DAG.getNode(ISD::SHL, DL, WideVT, DAG.getBitcast(WideVT, Op0),
30018 SDValue ShX = DAG.getNode(ISD::SHL, DL, VT, Op0,
30033 unsigned ShiftOpc = IsFSHR ? ISD::SRL : ISD::SHL;
30125 SDValue Res = DAG.getNode(ISD::SHL, DL, MVT::i32, Op0, HiShift);
30130 Res = DAG.getNode(ISD::SHL, DL, MVT::i32, Res, Amt);
30245 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, R,
30291 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL;
30361 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL;
30362 unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL;
30368 Amt = DAG.getNode(ISD::SHL, DL, ExtVT, Amt, DAG.getConstant(5, DL, ExtVT));
30401 bool LegalVarShifts = supportedVectorVarShift(VT, Subtarget, ISD::SHL) &&
30410 SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt);
30411 SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR);
30412 return DAG.getNode(ISD::OR, DL, VT, SHL, SRL);
31123 Hi = DAG.getNode(ISD::SHL, DL, MVT::i64, Hi,
31132 Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
31266 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), ShifterV);
31398 Op = DAG.getNode(ISD::SHL, DL, MVT::i32, Op,
32464 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
43836 case ISD::SHL: {
43837 // If we find a suitable source, a SHL becomes a KSHIFTL.
45332 SDValue Mask = DAG.getNode(ISD::SHL, dl, BCVT, MaskBit, MaskIdx);
46257 // Unlike general shift instructions (SHL/SRL), AVX2's VSHLV/VSRLV handle
46266 if ((LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SHL) &&
46278 if ((RHS.getOpcode() == ISD::SRL || RHS.getOpcode() == ISD::SHL) &&
46395 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And.getOperand(0), ShlAmt);
46568 // If Src came from a SHL (probably from an expanded SIGN_EXTEND_INREG), then
46570 if (Src.getOpcode() == ISD::SHL) {
47289 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
47628 Result = DAG.getNode(ISD::SHL, DL, VT, Result,
47697 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
47699 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
47880 // implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.
47956 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
47963 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
47985 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
47992 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
48003 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
48012 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
48032 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
48035 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
48114 supportedVectorVarShift(VT, Subtarget, ISD::SHL)) {
48189 // fold (SRA (SHL X, ShlConst), SraConst)
48190 // into (SHL (sext_in_reg X), ShlConst - SraConst)
48204 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
48229 return DAG.getNode(ISD::SHL, DL, VT, NN,
49461 if (ShiftedIndex.getOpcode() != ISD::SHL)
49927 SDValue Shift = DAG.getNode(ISD::SHL, dl, VT, Neg,
53786 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
55171 if ((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) &&
56419 // Special case: SHL/SRL AVX1 V4i64 by 32-bits can lower as a shuffle.
57517 Src = DAG.getNode(ISD::SHL, dl, NVT, Src, DAG.getConstant(16, dl, NVT));
57778 case ISD::SHL: return combineShiftLeft(N, DAG, Subtarget);
57956 if (Opc == ISD::SHL && VT.isVector() && VT.getVectorElementType() == MVT::i8)
57967 if ((Opc == ISD::MUL || Opc == ISD::SHL) && VT == MVT::i8)
57982 case ISD::SHL:
58085 case ISD::SHL: