Lines Matching defs:SBB
23947 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry.getValue(1));
24024 Opc == X86ISD::SBB || Opc == X86ISD::SMUL || Opc == X86ISD::UMUL ||
24181 SDValue SBB = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24184 return DAG.getNode(ISD::OR, DL, VT, SBB, Y);
26078 // ADC/SBB
26085 // ADC/SBB.
31839 SDValue Sum = DAG.getNode(IsAdd ? X86ISD::ADC : X86ISD::SBB, DL, VTs,
33814 NODE_NAME_CASE(SBB)
45620 // We have a more efficient lowering for "(X == 0) ? Y : -1" using SBB.
50426 /// then try to convert it to an ADC or SBB. This replaces TEST+SET+{ADD/SUB}
50427 /// with CMP+{ADC, SBB}.
50428 /// Also try (ADD/SUB)+(AND(SRL,1)) bit extraction pattern with BT+{ADC, SBB}.
50460 // -1 + SETAE --> -1 + (!CF) --> CF ? -1 : 0 --> SBB %eax, %eax
50461 // 0 - SETB --> 0 - (CF) --> CF ? -1 : 0 --> SBB %eax, %eax
50473 // -1 + SETBE (SUB A, B) --> -1 + SETAE (SUB B, A) --> SUB + SBB
50474 // 0 - SETA (SUB A, B) --> 0 - SETB (SUB B, A) --> SUB + SBB
50489 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
50511 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
50520 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL,
50541 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL,
50595 // Add the flags type for ADC/SBB nodes.
50601 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VTs, X,
50606 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, VTs, X,
50611 /// then try to convert it to an ADC or SBB. This replaces TEST+SET+{ADD/SUB}
50612 /// with CMP+{ADC, SBB}.
55346 return DAG.getNode(X86ISD::SBB, SDLoc(N), VTs, LHS, RHS, Flags);
55349 // Fold SBB(SUB(X,Y),0,Carry) -> SBB(X,Y,Carry)
55353 return DAG.getNode(X86ISD::SBB, SDLoc(N), N->getVTList(), LHS.getOperand(0),
55978 // Fold SUB(X,ADC(Y,0,W)) -> SBB(X,Y,W)
55982 return DAG.getNode(X86ISD::SBB, SDLoc(Op1), Op1->getVTList(), Op0,
55986 // Fold SUB(X,SBB(Y,Z,W)) -> SUB(ADC(X,Z,W),Y)
55988 if (Op1.getOpcode() == X86ISD::SBB && Op1->hasOneUse() &&
57775 case X86ISD::SBB: return combineSBB(N, DAG);