Lines Matching defs:RegVT

24757   MVT RegVT = Op.getSimpleValueType();
24758   assert(RegVT.isVector() && "We only custom lower vector loads.");
24759   assert(RegVT.isInteger() &&
24766   if (RegVT.getVectorElementType() == MVT::i1) {
24767     assert(EVT(RegVT) == Ld->getMemoryVT() && "Expected non-extending load");
24768     assert(RegVT.getVectorNumElements() <= 8 && "Unexpected VT");
24780     Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT,
51142   EVT RegVT = Ld->getValueType(0);
51150   if (!(RegVT.is128BitVector() || RegVT.is256BitVector()))
51178             RegVT.getFixedSizeInBits()) {
51191           unsigned NumBits = std::min(RegVT.getScalarSizeInBits(),
51199                   SDValue(User, 0), 0, DAG, SDLoc(N), RegVT.getSizeInBits());
51200               Extract = DAG.getBitcast(RegVT, Extract);
51216   EVT RegVT = Ld->getValueType(0);
51226   if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
51230        (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
51233     unsigned NumElems = RegVT.getVectorNumElements();
51254     SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2);
51260   if (Ext == ISD::NON_EXTLOAD && !Subtarget.hasAVX512() && RegVT.isVector() &&
51261       RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) {
51262     unsigned NumElts = RegVT.getVectorNumElements();
51269       SDValue BoolVec = DAG.getBitcast(RegVT, IntLoad);
51277       (RegVT.is128BitVector() || RegVT.is256BitVector())) {
51288               RegVT.getFixedSizeInBits()) {
51290                                            RegVT.getSizeInBits());
51291         Extract = DAG.getBitcast(RegVT, Extract);
51308       return DAG.getExtLoad(Ext, dl, RegVT, Ld->getChain(), Cast,