Lines Matching defs:Promote
203 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
258 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
260 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
261 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i8, Promote);
262 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
263 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i16, Promote);
273 // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
275 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
276 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i8, Promote);
289 // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
291 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
293 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i8, Promote);
305 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
307 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i8, Promote);
308 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
310 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i16, Promote);
401 // Promote the i8 variants and force them on up to i32 which has a shorter
673 setF16Action(MVT::f16, Promote);
674 setOperationAction(ISD::FADD, MVT::f16, Promote);
675 setOperationAction(ISD::FSUB, MVT::f16, Promote);
676 setOperationAction(ISD::FMUL, MVT::f16, Promote);
677 setOperationAction(ISD::FDIV, MVT::f16, Promote);
682 setOperationAction(ISD::STRICT_FADD, MVT::f16, Promote);
683 setOperationAction(ISD::STRICT_FSUB, MVT::f16, Promote);
684 setOperationAction(ISD::STRICT_FMUL, MVT::f16, Promote);
685 setOperationAction(ISD::STRICT_FDIV, MVT::f16, Promote);
686 setOperationAction(ISD::STRICT_FMA, MVT::f16, Promote);
687 setOperationAction(ISD::STRICT_FMINNUM, MVT::f16, Promote);
688 setOperationAction(ISD::STRICT_FMAXNUM, MVT::f16, Promote);
689 setOperationAction(ISD::STRICT_FMINIMUM, MVT::f16, Promote);
690 setOperationAction(ISD::STRICT_FMAXIMUM, MVT::f16, Promote);
691 setOperationAction(ISD::STRICT_FSQRT, MVT::f16, Promote);
692 setOperationAction(ISD::STRICT_FPOW, MVT::f16, Promote);
693 setOperationAction(ISD::STRICT_FLDEXP, MVT::f16, Promote);
694 setOperationAction(ISD::STRICT_FLOG, MVT::f16, Promote);
695 setOperationAction(ISD::STRICT_FLOG2, MVT::f16, Promote);
696 setOperationAction(ISD::STRICT_FLOG10, MVT::f16, Promote);
697 setOperationAction(ISD::STRICT_FEXP, MVT::f16, Promote);
698 setOperationAction(ISD::STRICT_FEXP2, MVT::f16, Promote);
699 setOperationAction(ISD::STRICT_FCEIL, MVT::f16, Promote);
700 setOperationAction(ISD::STRICT_FFLOOR, MVT::f16, Promote);
701 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f16, Promote);
702 setOperationAction(ISD::STRICT_FRINT, MVT::f16, Promote);
703 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Promote);
704 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Promote);
705 setOperationAction(ISD::STRICT_FROUND, MVT::f16, Promote);
706 setOperationAction(ISD::STRICT_FROUNDEVEN, MVT::f16, Promote);
707 setOperationAction(ISD::STRICT_FTRUNC, MVT::f16, Promote);
2221 setOperationAction(ISD::FREM, MVT::f16, Promote);
2222 setOperationAction(ISD::STRICT_FREM, MVT::f16, Promote);
2225 setOperationAction(ISD::STRICT_FROUND, MVT::f16, Promote);
2495 setOperationAction(Op, MVT::f32, Promote);
2503 setOperationAction(Op, MVT::f32, Promote);
19873 // Promote i32 to i64 and use a signed conversion on 64-bit targets.
21143 // Promote i32 to i64 and use a signed operation on 64-bit targets.
21166 // Promote i16 to i32 if we can use a SSE operation or the type is f128.
21310 // Promote result of FP_TO_*INT to at least 32 bits.
21316 // Promote conversions to unsigned 32-bit to 64-bit, because it will allow
32861 // Promote the input to 128 bits. Type legalization will turn this into
53681 // We do not want i16 CMOV's. Promote to i32 and truncate afterwards.
53727 if (SDValue Promote = PromoteMaskArithmetic(N0, dl, DAG, Subtarget))
53728 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Promote, N1);