Lines Matching defs:OpMask

39755   SmallVector<int, 64> OpMask;
39759   if (getTargetShuffleInputs(Op, OpDemandedElts, OpInputs, OpMask, OpUndef,
39774     OpMask.assign(NumElts, SM_SentinelUndef);
39775     std::iota(OpMask.begin(), OpMask.end(), ExtractIdx);
39785     unsigned OpMaskSize = OpMask.size();
39788       for (int &M : OpMask) {
39798     OpMask.append((NumSubVecs - 1) * OpMaskSize, SM_SentinelUndef);
39812       for (int i = 0, e = OpMask.size(); i != e; ++i) {
39813         int M = OpMask[i];
39816         UsedInputs.setBit(M / OpMask.size());
39823     resolveTargetShuffleFromZeroables(OpMask, OpUndef, OpZero,
39826     Mask = OpMask;
39829     resolveTargetShuffleFromZeroables(OpMask, OpUndef, OpZero);
39855     assert(((RootMask.size() > OpMask.size() &&
39856              RootMask.size() % OpMask.size() == 0) ||
39857             (OpMask.size() > RootMask.size() &&
39858              OpMask.size() % RootMask.size() == 0) ||
39859             OpMask.size() == RootMask.size()) &&
39867     assert(llvm::has_single_bit<uint32_t>(OpMask.size()) &&
39870     unsigned OpMaskSizeLog2 = llvm::countr_zero(OpMask.size());
39872     unsigned MaskWidth = std::max<unsigned>(OpMask.size(), RootMask.size());
39874         std::max<unsigned>(1, OpMask.size() >> RootMaskSizeLog2);
39914       if (OpMask[OpIdx] < 0) {
39917         Mask[i] = OpMask[OpIdx];
39922       unsigned OpMaskedIdx = OpRatio == 1 ? OpMask[OpIdx]
39923                                           : (OpMask[OpIdx] << OpRatioLog2) +
39927       int InputIdx = OpMask[OpIdx] / (int)OpMask.size();
42564   SmallVector<int, 64> OpMask;
42566   if (!getTargetShuffleInputs(Op, DemandedElts, OpInputs, OpMask, OpUndef,
42571   if (OpMask.size() != (unsigned)NumElts ||
42585       OpMask[i] = SM_SentinelUndef;
42587   if (isUndefInRange(OpMask, 0, NumElts)) {
42591   if (isUndefOrZeroInRange(OpMask, 0, NumElts)) {
42597     if (isSequentialOrUndefInRange(OpMask, 0, NumElts, Src * NumElts))
42610         int M = OpMask[i] - Lo;
58403     // Conditional OpMask regs (AVX512)