Lines Matching defs:N1
5842 SDValue N1 = N.getOperand(1);
5845 if (!getTargetConstantBitsFromNode(IsAndN ? N0 : N1, 8, UndefElts, EltBits,
5858 Ops.push_back(IsAndN ? N1 : N0);
5865 SDValue N1 = peekThroughBitcasts(N.getOperand(1));
5866 if (!N0.getValueType().isVector() || !N1.getValueType().isVector())
5872 APInt Demand1 = APInt::getAllOnes(N1.getValueType().getVectorNumElements());
5875 !getTargetShuffleInputs(N1, Demand1, SrcInputs1, SrcMask1, DAG,
5898 Ops.push_back(N1);
6086 SDValue N1 = N.getOperand(1);
6088 N1.getValueType().getVectorNumElements() == (NumElts / 2) &&
6100 (!(N1.isUndef() || EltsRHS.isZero()) &&
6101 DAG.ComputeNumSignBits(N1, EltsRHS, Depth + 1) <= NumBitsPerElt))
6111 if (N1.getOpcode() == X86ISD::VSRAI && N->isOnlyUserOf(N1.getNode()) &&
6112 N1.getConstantOperandAPInt(1) == NumBitsPerElt) {
6114 N1 = N1.getOperand(0);
6120 (!(N1.isUndef() || EltsRHS.isZero()) &&
6121 !DAG.MaskedValueIsZero(N1, ZeroMask, EltsRHS, Depth + 1)))
6125 bool IsUnary = (N0 == N1);
6129 Ops.push_back(N1);
10372 auto MatchPACK = [&](SDValue N1, SDValue N2, MVT PackVT) {
10375 N1 = peekThroughBitcasts(N1);
10377 unsigned NumBits1 = N1.getScalarValueSizeInBits();
10379 bool IsZero1 = llvm::isNullOrNullSplat(N1, /*AllowUndefs*/ false);
10381 if ((!N1.isUndef() && !IsZero1 && NumBits1 != NumSrcBits) ||
10386 if ((N1.isUndef() || IsZero1 || DAG.MaskedValueIsZero(N1, ZeroMask)) &&
10388 V1 = N1;
10395 bool IsAllOnes1 = llvm::isAllOnesOrAllOnesSplat(N1, /*AllowUndefs*/ false);
10397 if ((N1.isUndef() || IsZero1 || IsAllOnes1 ||
10398 DAG.ComputeNumSignBits(N1) > NumPackedBits) &&
10401 V1 = N1;
12432 SDValue N1, ArrayRef<int> Mask,
12441 N1.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
12442 N0.getOperand(0) != N1.getOperand(0) ||
12443 !N0.hasOneUse() || !N1.hasOneUse())
12452 // if the extract of the low half is N1.
12456 const APInt &ExtIndex1 = N1.getConstantOperandAPInt(1);
18214 SDValue N1 = Op.getOperand(1);
18222 DAG.getBitcast(MVT::i16, N1), N2);
18242 SDValue EltSplat = DAG.getSplatBuildVector(VT, dl, N1);
18249 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0.
18258 bool IsZeroElt = X86::isZeroNode(N1);
18259 bool IsAllOnesElt = VT.isInteger() && llvm::isAllOnesConstant(N1);
18298 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
18310 // FIXME: relax the profitability check iff all N1 uses are insertions.
18314 X86::mayFoldLoad(N1, Subtarget)))) {
18315 SDValue N1SplatVec = DAG.getSplatBuildVector(VT, dl, N1);
18329 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
18341 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
18342 return getShuffleVectorZeroOrUndef(N1, 0, true, Subtarget, DAG);
18348 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, N1);
18350 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShufVT, N1);
18351 N1 = getShuffleVectorZeroOrUndef(N1, 0, true, Subtarget, DAG);
18352 return DAG.getBitcast(VT, N1);
18369 assert(N1.getValueType() != MVT::i32 && "Unexpected VT");
18370 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
18372 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
18387 if (IdxVal == 0 && (!MinSize || !X86::mayFoldLoad(N1, Subtarget))) {
18395 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
18396 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1,
18400 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
18401 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1,
26643 SDNode *N1 = DAG.getMachineNode(
26645 Chain = SDValue(N1, 0);
26650 LO = DAG.getCopyFromReg(Chain, DL, X86::RAX, MVT::i64, SDValue(N1, 1));
26654 LO = DAG.getCopyFromReg(Chain, DL, X86::EAX, MVT::i32, SDValue(N1, 1));
31929 SDValue N1 = InOp.getOperand(1);
31930 if ((ISD::isBuildVectorAllZeros(N1.getNode()) && FillWithZeroes) ||
31931 N1.isUndef()) {
32704 SDValue N1 = DAG.getConstant(SplatVal, dl, ResVT);
32705 SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1);
40333 SDValue N1 = V.getOperand(1);
40337 X86::mayFoldLoad(peekThroughOneUseBitcasts(N1), Subtarget))
40340 return DAG.getNode(X86ISD::SHUFP, DL, VT, N1, N0,
40354 SDValue N1 = N.getOperand(1);
40356 if (N0 == N1) {
40361 return DAG.getNode(X86ISD::SHUFP, DL, VT, NewSHUFP, N1,
40363 } else if (SDValue NewSHUFP = commuteSHUFP(N, N1)) {
40377 combineBlendOfPermutes(MVT VT, SDValue N0, SDValue N1, ArrayRef<int> BlendMask,
40381 if (!N0.hasOneUse() || !N1.hasOneUse())
40386 SDValue BC1 = peekThroughOneUseBitcasts(N1);
40578 SDValue N1 = peekThroughOneUseBitcasts(N.getOperand(1));
40580 if (TLI.isBinOp(SrcOpcode) && N1.getOpcode() == SrcOpcode &&
40581 N0.getValueType() == N1.getValueType() &&
40583 IsSafeToMoveShuffle(N1, SrcOpcode)) {
40585 SDValue Op10 = peekThroughOneUseBitcasts(N1.getOperand(0));
40587 SDValue Op11 = peekThroughOneUseBitcasts(N1.getOperand(1));
40613 if (isUnaryOp(SrcOpcode) && N1.getOpcode() == SrcOpcode &&
40614 N0.getValueType() == N1.getValueType() &&
40616 IsSafeToMoveShuffle(N1, SrcOpcode)) {
40618 SDValue Op10 = peekThroughOneUseBitcasts(N1.getOperand(0));
41038 SDValue N1 = N.getOperand(1);
41041 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) {
41044 if (N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
41054 N1.getOperand(0),
41063 if (N0.hasOneUse() && N1.hasOneUse()) {
41067 SDValue RHS = peekThroughOneUseBitcasts(N1);
41134 SDValue N1 = N.getOperand(1);
41140 SDValue Res = DAG.getNode(X86ISD::VPERMI, DL, SrcVT, Src, N1);
41224 SDValue N1 = N.getOperand(1);
41239 DAG.getBitcast(VT, V.getOperand(0)), N1);
41257 SDValue N1 = N.getOperand(1);
41260 // MOVS*(N0, OP(N0, N1)) --> MOVS*(N0, SCALAR_TO_VECTOR(OP(N0[0], N1[0])))
41261 // If commutable, allow OP(N1[0], N0[0]).
41262 unsigned Opcode1 = N1.getOpcode();
41265 SDValue N10 = N1.getOperand(0);
41266 SDValue N11 = N1.getOperand(1);
41696 SDValue N1 = N->getOperand(1);
41700 N1.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
41701 N1.getNumOperands() != 2 || !N0.getOperand(1).isUndef() ||
41702 !N1.getOperand(1).isUndef())
41715 N1.getOperand(0));
42201 SDValue N1 = Op.getOperand(1);
42211 if (SimplifyDemandedVectorElts(N1, DemandedRHS, RHSUndef, RHSZero, TLO,
42222 SDValue NewN1 = SimplifyMultipleUseDemandedVectorElts(N1, DemandedRHS,
42226 NewN1 = NewN1 ? NewN1 : N1;
42238 SDValue N1 = Op.getOperand(1);
42248 if (SimplifyDemandedVectorElts(N1, DemandedRHS, RHSUndef, RHSZero, TLO,
42256 if (N0 != N1 && !DemandedElts.isAllOnes()) {
42259 SDValue NewN1 = SimplifyMultipleUseDemandedVectorElts(N1, DemandedRHS,
42263 NewN1 = NewN1 ? NewN1 : N1;
43831 if (SDValue N1 = combineBitcastToBoolVector(VT, V.getOperand(1), DL, DAG,
43833 return DAG.getNode(Opc, DL, VT, N0, N1);
47573 SDValue N1 = N->getOperand(1);
47583 SDValue NewN1 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N1);
47737 SDValue N1 = N->getOperand(1);
47744 (N1.getOpcode() == ISD::ZERO_EXTEND &&
47745 N1.getOperand(0).getScalarValueSizeInBits() <= 8)) ||
47748 (N1.getOpcode() == ISD::SIGN_EXTEND &&
47749 N1.getOperand(0).getScalarValueSizeInBits() <= 8))))
47757 (N1.getOpcode() == ISD::SIGN_EXTEND &&
47758 N1.getOperand(0).getValueSizeInBits() > 128))
47762 if (DAG.ComputeMaxSignificantBits(N1) > 16 ||
47804 SDValue ZeroN1 = GetZeroableOp(N1);
47808 N1 = ZeroN1 ? ZeroN1 : N1;
47819 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMADDWDBuilder);
47836 SDValue N1 = N->getOperand(1);
47841 DAG.ComputeNumSignBits(N1) > 32) {
47846 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMULDQBuilder,
47852 if (DAG.MaskedValueIsZero(N0, Mask) && DAG.MaskedValueIsZero(N1, Mask)) {
47857 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMULUDQBuilder,
48105 SDValue N1 = N->getOperand(1);
48106 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
48120 sd_match(Cond, m_SetCC(m_Specific(N1), m_SpecificInt(EltSizeInBits),
48122 return DAG.getNode(X86ISD::VSHLV, DL, VT, N00, N1);
48126 sd_match(Cond, m_SetCC(m_Specific(N1), m_SpecificInt(EltSizeInBits),
48128 return DAG.getNode(X86ISD::VSHLV, DL, VT, N01, N1);
48173 SDValue N1 = N->getOperand(1);
48184 if (sd_match(N1, m_UMin(m_Value(ShrAmtVal),
48203 if (VT.isVector() || N1.getOpcode() != ISD::Constant ||
48211 APInt SraConst = N1->getAsAPIntVal();
48212 EVT CVT = N1.getValueType();
48242 SDValue N1 = N->getOperand(1);
48259 sd_match(Cond, m_SetCC(m_Specific(N1), m_SpecificInt(EltSizeInBits),
48261 return DAG.getNode(X86ISD::VSRLV, DL, VT, N00, N1);
48265 sd_match(Cond, m_SetCC(m_Specific(N1), m_SpecificInt(EltSizeInBits),
48267 return DAG.getNode(X86ISD::VSRLV, DL, VT, N01, N1);
48283 auto *ShiftC = dyn_cast<ConstantSDNode>(N1);
48307 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
48321 SDValue N1 = N->getOperand(1);
48327 N->isOnlyUserOf(N1.getNode()) ? peekThroughOneUseBitcasts(N1) : N1;
48466 SDValue N1 = N->getOperand(1);
48471 N1.getScalarValueSizeInBits() == SrcBitsPerElt &&
48480 (N1.isUndef() || N->isOnlyUserOf(N1.getNode())) &&
48484 getTargetConstantBitsFromNode(N1, SrcBitsPerElt, UndefElts1, EltBits1,
48538 (N1.isUndef() || DAG.ComputeNumSignBits(N1) == SrcBitsPerElt)) {
48540 SDValue Not1 = N1.isUndef() ? N1 : IsNOT(N1, DAG);
48554 N0.getOpcode() == ISD::TRUNCATE && N1.isUndef() && VT == MVT::v16i8 &&
48579 if (N1.getOpcode() == ExtOpc &&
48580 N1.getOperand(0).getValueType().is64BitVector() &&
48581 N1.getOperand(0).getScalarValueSizeInBits() == DstBitsPerElt) {
48582 Src1 = N1.getOperand(0);
48584 if ((Src0 || N0.isUndef()) && (Src1 || N1.isUndef())) {
48594 if (N0.getOpcode() == VecInRegOpc && N1.isUndef() &&
48664 SDValue N1 = N->getOperand(1);
48673 if (getTargetConstantBitsFromNode(N1, 64, UndefElts, EltBits,
48699 SDValue N1 = N->getOperand(1);
48703 assert(N1.getValueType() == MVT::i8 && "Unexpected shift amount type");
48780 Src = DAG.getNode(X86ISD::VSHLI, DL, VT, Src, N1);
48781 Src = DAG.getNode(X86ISD::VSRAI, DL, VT, Src, N1);
48828 DAG.getBitcast(VT, BC.getOperand(0)), N1);
48890 SDValue N1 = N->getOperand(1);
48892 SDValue CMP1 = N1.getOperand(1);
48928 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
48997 SDValue N1 = N->getOperand(1);
49001 Y = N1;
49002 } else if (SDValue Not = IsNOT(N1, DAG)) {
49060 SDValue N1 = N->getOperand(1);
49065 Y = N1;
49066 } else if (SDValue Not = GetNot(N1)) {
49115 SDValue N1 = N.getOperand(1);
49135 if (SDValue NN1 = PromoteMaskArithmetic(N1, DL, VT, DAG, Depth + 1))
49136 N1 = NN1;
49139 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE &&
49140 N1.getOperand(0).getValueType() == VT;
49142 N1 = N1.getOperand(0);
49144 DAG.FoldConstantArithmetic(ISD::ZERO_EXTEND, DL, VT, {N1}))
49145 N1 = Cst;
49150 return DAG.getNode(N.getOpcode(), DL, VT, N0, N1);
49208 SDValue N1 = N->getOperand(1);
49211 if (!((N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) ||
49212 (N0.getOpcode() == ISD::SETCC && N1.getOpcode() == ISD::SETCC)))
49216 SDValue N10 = N1.getOperand(0);
49233 !N1.hasOneUse())
49237 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1.getOperand(2))->get();
49254 SDValue N11 = N1.getOperand(1);
49273 SDValue N1 = N->getOperand(1);
49277 N1.getOpcode() != X86ISD::MOVMSK || !N1.hasOneUse())
49281 SDValue Vec1 = N1.getOperand(0);
49308 SDValue N1 = N->getOperand(1);
49312 if (!N0.hasOneUse() || !N1.hasOneUse())
49317 SDValue BC1 = peekThroughOneUseBitcasts(N1);
49351 SDValue N1 = N->getOperand(1);
49355 if (!N0.hasOneUse() || !N1.hasOneUse())
49360 N1 = peekThroughOneUseBitcasts(N1);
49362 if (N0.getOpcode() != X86ISD::PACKSS || N1.getOpcode() != X86ISD::PACKSS)
49366 if (DstVT != N1.getSimpleValueType())
49375 DAG.ComputeNumSignBits(N1.getOperand(0)) != NumSrcBits ||
49376 DAG.ComputeNumSignBits(N1.getOperand(1)) != NumSrcBits)
49380 SDValue LHS = DAG.getNode(Opc, DL, SrcVT, N0.getOperand(0), N1.getOperand(0));
49381 SDValue RHS = DAG.getNode(Opc, DL, SrcVT, N0.getOperand(1), N1.getOperand(1));
49855 SDValue N1 = N->getOperand(1);
49865 DAG.getBitcast(MVT::v4f32, N1)));
49869 if (VT == MVT::i64 && Subtarget.is64Bit() && !isa<ConstantSDNode>(N1)) {
49871 if (DAG.MaskedValueIsZero(N1, HiMask) ||
49874 SDValue RHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, N1);
49912 ConstantSDNode *N1C = isConstOrConstSplat(N1, /*AllowUndefs*/ true,
49929 return DAG.getNode(ISD::AND, dl, VT, Shift, N1);
49973 if (VT.isVector() && getTargetConstantFromNode(N1)) {
49977 DAG.ComputeNumSignBits(N1) == VT.getScalarSizeInBits() &&
49979 SDValue MaskMul = DAG.getNode(ISD::AND, dl, VT, N0.getOperand(1), N1);
49986 if (isOneConstant(N1) && N0->hasOneUse()) {
50052 std::tie(Bits0, Elts0) = GetDemandedMasks(N1);
50056 TLI.SimplifyDemandedVectorElts(N1, Elts1, DCI) ||
50058 TLI.SimplifyDemandedBits(N1, Bits1, Elts1, DCI)) {
50065 SDValue NewN1 = TLI.SimplifyMultipleUseDemandedBits(N1, Bits1, Elts1, DAG);
50068 NewN1 ? NewN1 : N1);
50075 SDValue BitMask = N1;
50127 SDValue N1 = peekThroughBitcasts(N->getOperand(1));
50128 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
50134 !N0.getOperand(1).hasOneUse() || !N1.getOperand(1).hasOneUse()))
50144 if (!getTargetConstantBitsFromNode(N1.getOperand(1), 8, UndefElts1, EltBits1,
50167 SDValue C = DAG.getBitcast(OpVT, N1.getOperand(0));
50177 DAG.getBitcast(VT, N1.getOperand(0)));
50187 SDValue N1 = N->getOperand(1);
50190 if (N1.getOpcode() == ISD::AND)
50191 std::swap(N0, N1);
50194 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != X86ISD::ANDNP)
50197 Mask = N1.getOperand(0);
50198 X = N1.getOperand(1);
50405 SDValue N1 = Node->getOperand(1);
50406 if (N1->getOpcode() != ISD::AND || !N1->hasOneUse())
50412 SDValue N10 = N1->getOperand(0);
50413 SDValue N11 = N1->getOperand(1);
50633 static SDValue combineOrXorWithSETCC(SDNode *N, SDValue N0, SDValue N1,
50646 if (auto *N1C = dyn_cast<ConstantSDNode>(N1)) {
50652 if (SDValue R = combineAddOrSubToADCOrSBB(IsSub, DL, VT, N1, N0, DAG))
50662 ISD::isBuildVectorAllOnes(N1.getNode())) {
50686 SDValue N1 = N->getOperand(1);
50696 DAG.getBitcast(MVT::v4f32, N1)));
50758 if (auto *CN = dyn_cast<ConstantSDNode>(N1)) {
50778 if (N0.getOpcode() == X86ISD::KSHIFTL || N1.getOpcode() == X86ISD::KSHIFTL) {
50782 if (NumElts >= 16 && N1.getOpcode() == X86ISD::KSHIFTL &&
50783 N1.getConstantOperandAPInt(1) == HalfElts &&
50788 extractSubVector(N1.getOperand(0), 0, DAG, dl, HalfElts));
50792 DAG.MaskedVectorIsZero(N1, UpperElts)) {
50795 extractSubVector(N1, 0, DAG, dl, HalfElts),
50823 if (SimplifyUndemandedElts(N0, N1) || SimplifyUndemandedElts(N1, N0)) {
50835 if (SDValue R = combineOrXorWithSETCC(N, N0, N1, DAG))
50852 SDValue N1 = N->getOperand(1);
50859 if (!isOneConstant(N1))
51932 auto GetShuffle = [&](SDValue Op, SDValue &N0, SDValue &N1,
51952 N1 = SrcOps.size() > 1 ? SrcOps[1] : SDValue();
51957 std::tie(N0, N1) = DAG.SplitVector(SrcOps[0], SDLoc(Op));
52347 auto TruncateArithmetic = [&](SDValue N0, SDValue N1) {
52349 SDValue Trunc1 = DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
52500 SDValue N1 = SSatVal.getOperand(1);
52502 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
52507 SDValue N10 = N1.getOperand(0);
52508 SDValue N11 = N1.getOperand(1);
52579 // N0 indices be the even element. N1 indices must be the next odd element.
52998 SDValue N1 = N->getOperand(1);
53001 N1.getOpcode() != ISD::CTLZ_ZERO_UNDEF)
53007 if (N1.getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
53008 OpCTLZ = N1;
53014 OpSizeTM1 = N1;
53045 SDValue N1 = N->getOperand(1);
53054 DAG.getBitcast(MVT::v4f32, N1)));
53081 if (SDValue R = combineOrXorWithSETCC(N, N0, N1, DAG))
53089 if (llvm::isAllOnesConstant(N1) && N0.getOpcode() == ISD::BITCAST &&
53099 if (ISD::isBuildVectorAllOnes(N1.getNode()) && VT.isVector() &&
53115 auto *N1C = dyn_cast<ConstantSDNode>(N1);
53121 DAG.getNode(ISD::XOR, DL, VT, RHS, N1));
53164 SDValue N1 = N->getOperand(1);
53175 N1 = DAG.getNode(ISD::XOR, DL, VT, N1, SignMask);
53177 DAG.getNode(ISD::AVGCEILU, DL, VT, N0, N1), SignMask);
53224 SDValue N1 = N->getOperand(1);
53243 return DAG.getNode(X86ISD::FANDN, DL, VT, N0.getOperand(0), N1);
53246 if (N1.getOpcode() == X86ISD::FXOR && isAllOnesConstantFP(N1.getOperand(1)))
53247 return DAG.getNode(X86ISD::FANDN, DL, VT, N1.getOperand(0), N0);
53465 SDValue N1 = N->getOperand(1);
53473 if (N0.isUndef() || N1.isUndef())
53478 return N1;
53481 if (ISD::isBuildVectorAllZeros(N1.getNode()))
53485 if (ISD::isBuildVectorAllOnes(N1.getNode()))
53490 return DAG.getNode(ISD::AND, DL, VT, DAG.getBitcast(VT, Not), N1);
53494 if (N1->hasOneUse())
53495 if (SDValue Not = IsNOT(N1, DAG))
53505 if (getTargetConstantBitsFromNode(N1, EltSizeInBits, Undefs1, EltBits1,
53523 return DAG.getNode(ISD::AND, DL, VT, Not, N1);
53562 std::tie(Bits0, Elts0) = GetDemandedMasks(N1);
53567 TLI.SimplifyDemandedVectorElts(N1, Elts1, DCI) ||
53569 TLI.SimplifyDemandedBits(N1, Bits1, Elts1, DCI)) {
53581 SDValue N1 = N->getOperand(1);
53584 unsigned BitWidth = N1.getValueSizeInBits();
53586 if (DAG.getTargetLoweringInfo().SimplifyDemandedBits(N1, DemandedMask, DCI)) {
53642 SDValue N1 = N->getOperand(1);
53643 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
53677 CMovOp0 = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, DstVT, CMovOp0, N1);
53678 CMovOp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, DstVT, CMovOp1, N1);
53706 SDValue N1 = N->getOperand(1);
53707 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
53728 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Promote, N1);
53732 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, N00, N1);
54229 auto MatchOrCmpEq = [&](SDValue N0, SDValue N1) {
54231 if (N0.getOperand(0) == N1)
54232 return DAG.getNode(ISD::AND, DL, OpVT, DAG.getNOT(DL, N1, OpVT),
54234 if (N0.getOperand(1) == N1)
54235 return DAG.getNode(ISD::AND, DL, OpVT, DAG.getNOT(DL, N1, OpVT),
54247 auto MatchAndCmpEq = [&](SDValue N0, SDValue N1) {
54249 if (N0.getOperand(0) == N1)
54250 return DAG.getNode(ISD::AND, DL, OpVT, N1,
54252 if (N0.getOperand(1) == N1)
54253 return DAG.getNode(ISD::AND, DL, OpVT, N1,
55319 auto MatchGeneric = [&](SDValue N0, SDValue N1, bool Negate) {
55320 SDValue Ops[] = {N0, N1};
55510 SDValue N1 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Mul.getOperand(1));
55520 return SplitOpsAndApply(DAG, Subtarget, DL, VT, { N0, N1 }, PMADDBuilder);
55526 static SDValue matchPMADDWD_2(SelectionDAG &DAG, SDValue N0, SDValue N1,
55532 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
55542 SDValue N10 = N1.getOperand(0);
55543 SDValue N11 = N1.getOperand(1);
55605 // N0 indices be the even element. N1 indices must be the next odd element.
55666 static SDValue combineAddOfPMADDWD(SelectionDAG &DAG, SDValue N0, SDValue N1,
55668 if (N0.getOpcode() != N1.getOpcode() || N0.getOpcode() != X86ISD::VPMADDWD)
55684 DAG.MaskedValueIsZero(N1.getOperand(0), DemandedBits, DemandedHiElts) ||
55685 DAG.MaskedValueIsZero(N1.getOperand(1), DemandedBits, DemandedHiElts);
55700 DAG.getVectorShuffle(OpVT, DL, N0.getOperand(0), N1.getOperand(0), Mask);
55702 DAG.getVectorShuffle(OpVT, DL, N0.getOperand(1), N1.getOperand(1), Mask);
55850 SDValue N1 = N->getOperand(1);
55852 if (N1.getOpcode() != X86ISD::CMOV || !N1.hasOneUse())
55855 X86::CondCode CC = (X86::CondCode)N1.getConstantOperandVal(2);
55860 SDValue Cond = N1.getOperand(3);
55869 SDValue FalseOp = N1.getOperand(0);
55870 SDValue TrueOp = N1.getOperand(1);
55880 N1.getOperand(2), Cond);
58103 SDValue N1 = Op.getOperand(1);
58105 if (X86::mayFoldLoad(N1, Subtarget) &&
58107 (Op.getOpcode() != ISD::MUL && IsFoldableRMW(N1, Op))))
58110 ((Commute && !isa<ConstantSDNode>(N1)) ||
58114 (Commute && IsFoldableAtomicRMW(N1, Op)))