Lines Matching defs:N01
48117 SDValue N01 = N0.getOperand(2);
48119 if (ISD::isConstantSplatVectorAllZeros(N01.getNode()) &&
48128 return DAG.getNode(X86ISD::VSHLV, DL, VT, N01, N1);
48209 SDValue N01 = N0.getOperand(1);
48210 APInt ShlConst = N01->getAsAPIntVal();
48214 if (CVT != N01.getValueType())
48256 SDValue N01 = N0.getOperand(2);
48258 if (ISD::isConstantSplatVectorAllZeros(N01.getNode()) &&
48267 return DAG.getNode(X86ISD::VSRLV, DL, VT, N01, N1);
49247 // logic (setcc N00, N01), (setcc N10, N11) -->
49248 // extelt (logic (setcc (s2v N00), (s2v N01)), setcc (s2v N10), (s2v N11))), 0
49253 SDValue N01 = N0.getOperand(1);
49256 SDValue Vec01 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, N01);
50411 SDValue N01 = N0->getOperand(1);
50414 if (SDValue Result = foldMaskedMergeImpl(N00, N01, N10, N11, DL, DAG))
50416 if (SDValue Result = foldMaskedMergeImpl(N01, N00, N10, N11, DL, DAG))
50418 if (SDValue Result = foldMaskedMergeImpl(N10, N11, N00, N01, DL, DAG))
50420 if (SDValue Result = foldMaskedMergeImpl(N11, N10, N00, N01, DL, DAG))
52506 SDValue N01 = N0.getOperand(1);
52512 if (N01.getOpcode() == ISD::ZERO_EXTEND)
52513 std::swap(N00, N01);
52519 N01.getOpcode() != ISD::SIGN_EXTEND ||
52526 N01 = N01.getOperand(0);
52532 N01.getValueType().getVectorElementType() != MVT::i8 ||
52539 N01.getOpcode() != ISD::BUILD_VECTOR ||
52544 // N00/N10 are zero extended. N01/N11 are sign extended.
52555 SDValue N01Elt = N01.getOperand(i);
54175 SDValue N01 = N0.getOperand(1);
54179 (N01.isUndef() || DAG.MaskedValueIsZero(N01, ZeroMask))) {
54180 return concatSubVectors(N00, N01, DAG, dl);
55541 SDValue N01 = N0.getOperand(1);
55548 N01.getOpcode() != ISD::SIGN_EXTEND ||
55555 N01 = N01.getOperand(0);
55561 if (InVT.getVectorElementType() != MVT::i16 || N01.getValueType() != InVT ||
55567 N01.getOpcode() != ISD::BUILD_VECTOR ||
55581 SDValue N01Elt = N01.getOperand(i);