Lines Matching defs:N00
44002 SDValue N00 = N0.getOperand(0);
44003 SDLoc dl(N00);
44004 N00 = LowUndef ? DAG.getAnyExtOrTrunc(N00, dl, MVT::i32)
44005 : DAG.getZExtOrTrunc(N00, dl, MVT::i32);
44006 return DAG.getNode(X86ISD::MMX_MOVW2D, dl, VT, N00);
44022 SDValue N00 = N0.getOperand(0);
44023 if (N00.getValueType().is128BitVector())
44024 return DAG.getNode(X86ISD::MOVDQ2Q, SDLoc(N00), VT,
44025 DAG.getBitcast(MVT::v2i64, N00));
45382 SDValue N00 = N0.getOperand(0);
45383 EVT SclVT = N00.getValueType();
45401 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, BroadcastVT, N00);
45417 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, BroadcastVT, N00);
45425 SDValue Scl = DAG.getAnyExtOrTrunc(N00, DL, SVT);
48116 SDValue N00 = N0.getOperand(1);
48122 return DAG.getNode(X86ISD::VSHLV, DL, VT, N00, N1);
48125 if (ISD::isConstantSplatVectorAllZeros(N00.getNode()) &&
48137 SDValue N00 = N0.getOperand(0);
48152 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
48154 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
48155 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
48157 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
48158 N00.getOpcode() == ISD::ANY_EXTEND) &&
48159 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
48160 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
48163 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
48208 SDValue N00 = N0.getOperand(0);
48225 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N00, DAG.getValueType(SVT));
48255 SDValue N00 = N0.getOperand(1);
48261 return DAG.getNode(X86ISD::VSRLV, DL, VT, N00, N1);
48264 if (ISD::isConstantSplatVectorAllZeros(N00.getNode()) &&
49215 SDValue N00 = N0.getOperand(0);
49217 EVT N00Type = N00.getValueType();
49228 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
49247 // logic (setcc N00, N01), (setcc N10, N11) -->
49248 // extelt (logic (setcc (s2v N00), (s2v N01)), setcc (s2v N10), (s2v N11))), 0
49255 SDValue Vec00 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, N00);
50410 SDValue N00 = N0->getOperand(0);
50414 if (SDValue Result = foldMaskedMergeImpl(N00, N01, N10, N11, DL, DAG))
50416 if (SDValue Result = foldMaskedMergeImpl(N01, N00, N10, N11, DL, DAG))
50418 if (SDValue Result = foldMaskedMergeImpl(N10, N11, N00, N01, DL, DAG))
50420 if (SDValue Result = foldMaskedMergeImpl(N11, N10, N00, N01, DL, DAG))
52505 SDValue N00 = N0.getOperand(0);
52513 std::swap(N00, N01);
52518 if (N00.getOpcode() != ISD::ZERO_EXTEND ||
52525 N00 = N00.getOperand(0);
52531 if (N00.getValueType().getVectorElementType() != MVT::i8 ||
52538 if (N00.getOpcode() != ISD::BUILD_VECTOR ||
52544 // N00/N10 are zero extended. N01/N11 are sign extended.
52554 SDValue N00Elt = N00.getOperand(i);
53717 SDValue N00 = N0.getOperand(0);
53721 if (N00.getOpcode() == ISD::LOAD && Subtarget.hasInt256())
53722 if (!ISD::isNormalLoad(N00.getNode()))
53730 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
53732 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, N00, N1);
54174 SDValue N00 = N0.getOperand(0);
54176 unsigned NumSrcEltBits = N00.getScalarValueSizeInBits();
54178 if ((N00.isUndef() || DAG.MaskedValueIsZero(N00, ZeroMask)) &&
54180 return concatSubVectors(N00, N01, DAG, dl);
55540 SDValue N00 = N0.getOperand(0);
55547 if (N00.getOpcode() != ISD::SIGN_EXTEND ||
55554 N00 = N00.getOperand(0);
55560 EVT InVT = N00.getValueType();
55566 if (N00.getOpcode() != ISD::BUILD_VECTOR ||
55579 for (unsigned i = 0; i != N00.getNumOperands(); ++i) {
55580 SDValue N00Elt = N00.getOperand(i);