Lines Matching defs:N0
5841 SDValue N0 = N.getOperand(0);
5845 if (!getTargetConstantBitsFromNode(IsAndN ? N0 : N1, 8, UndefElts, EltBits,
5858 Ops.push_back(IsAndN ? N1 : N0);
5864 SDValue N0 = peekThroughBitcasts(N.getOperand(0));
5866 if (!N0.getValueType().isVector() || !N1.getValueType().isVector())
5871 APInt Demand0 = APInt::getAllOnes(N0.getValueType().getVectorNumElements());
5873 if (!getTargetShuffleInputs(N0, Demand0, SrcInputs0, SrcMask0, DAG,
5897 Ops.push_back(N0);
6085 SDValue N0 = N.getOperand(0);
6087 assert(N0.getValueType().getVectorNumElements() == (NumElts / 2) &&
6098 if ((!(N0.isUndef() || EltsLHS.isZero()) &&
6099 DAG.ComputeNumSignBits(N0, EltsLHS, Depth + 1) <= NumBitsPerElt) ||
6106 if (N0.getOpcode() == X86ISD::VSRAI && N->isOnlyUserOf(N0.getNode()) &&
6107 N0.getConstantOperandAPInt(1) == NumBitsPerElt) {
6109 N0 = N0.getOperand(0);
6118 if ((!(N0.isUndef() || EltsLHS.isZero()) &&
6119 !DAG.MaskedValueIsZero(N0, ZeroMask, EltsLHS, Depth + 1)) ||
6125 bool IsUnary = (N0 == N1);
6127 Ops.push_back(N0);
12431 static SDValue lowerShuffleOfExtractsAsVperm(const SDLoc &DL, SDValue N0,
12434 MVT VT = N0.getSimpleValueType();
12440 if (N0.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
12442 N0.getOperand(0) != N1.getOperand(0) ||
12443 !N0.hasOneUse() || !N1.hasOneUse())
12446 SDValue WideVec = N0.getOperand(0);
12455 const APInt &ExtIndex0 = N0.getConstantOperandAPInt(1);
18213 SDValue N0 = Op.getOperand(0);
18221 DAG.getBitcast(IVT, N0),
18249 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0.
18250 return DAG.getSelectCC(dl, IdxSplat, Indices, EltSplat, N0,
18272 return DAG.getNode(ISD::OR, dl, VT, N0, CstVector);
18283 return DAG.getVectorShuffle(VT, dl, N0, CstVector, BlendMask);
18299 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec,
18319 return DAG.getVectorShuffle(VT, dl, N0, N1SplatVec, BlendMask);
18323 SDValue V = extract128BitVector(N0, IdxVal, DAG, dl);
18333 return insert128BitVector(N0, V, IdxVal, DAG, dl);
18338 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(N0.getNode())) {
18372 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
18396 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1,
18401 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1,
19614 SDValue N0 = Op.getOperand(IsStrict ? 1 : 0);
19615 assert(N0.getSimpleValueType() == MVT::v2i32 && "Unexpected input type");
19623 N0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
19626 {Op.getOperand(0), N0});
19634 N0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
19638 {Op.getOperand(0), N0});
19639 return DAG.getNode(X86ISD::CVTUI2P, DL, MVT::v2f64, N0);
19646 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i64, N0);
19820 SDValue N0 = Op.getOperand(OpNo);
19821 MVT SrcVT = N0.getSimpleValueType();
21810 SDValue N0 = Op.getOperand(0);
21814 // N0 += copysign(nextafter(0.5, 0.0), N0)
21822 DAG.getConstantFP(Point5Pred, dl, VT), N0);
21823 N0 = DAG.getNode(ISD::FADD, dl, VT, N0, Adder);
21826 return DAG.getNode(ISD::FTRUNC, dl, VT, N0);
21962 SDValue N0 = Op.getOperand(0);
21966 MVT OpVT = N0.getSimpleValueType();
21972 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, N0);
28097 SDValue N0 = Op.getOperand(0);
28105 Op = DAG.getNode(X86ISD::BSF, dl, VTs, N0);
28108 if (DAG.isKnownNeverZero(N0))
28213 SDValue N0 = Op.getOperand(0);
28215 DAG.getConstant(0, DL, VT), N0);
28216 SDValue Ops[] = {N0, Neg, DAG.getTargetConstant(X86::COND_NS, DL, MVT::i8),
32703 SDValue N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Ops0);
32705 SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1);
40332 SDValue N0 = V.getOperand(0);
40336 if (!X86::mayFoldLoad(peekThroughOneUseBitcasts(N0), Subtarget) ||
40340 return DAG.getNode(X86ISD::SHUFP, DL, VT, N1, N0,
40353 SDValue N0 = N.getOperand(0);
40356 if (N0 == N1) {
40357 if (SDValue NewSHUFP = commuteSHUFP(N, N0))
40360 } else if (SDValue NewSHUFP = commuteSHUFP(N, N0)) {
40364 return DAG.getNode(X86ISD::SHUFP, DL, VT, N0, NewSHUFP,
40377 combineBlendOfPermutes(MVT VT, SDValue N0, SDValue N1, ArrayRef<int> BlendMask,
40381 if (!N0.hasOneUse() || !N1.hasOneUse())
40385 SDValue BC0 = peekThroughOneUseBitcasts(N0);
40531 SDValue N0 = peekThroughOneUseBitcasts(N.getOperand(0));
40532 unsigned SrcOpcode = N0.getOpcode();
40533 if (TLI.isBinOp(SrcOpcode) && IsSafeToMoveShuffle(N0, SrcOpcode)) {
40534 SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0));
40535 SDValue Op01 = peekThroughOneUseBitcasts(N0.getOperand(1));
40550 EVT OpVT = N0.getValueType();
40577 SDValue N0 = peekThroughOneUseBitcasts(N.getOperand(0));
40579 unsigned SrcOpcode = N0.getOpcode();
40581 N0.getValueType() == N1.getValueType() &&
40582 IsSafeToMoveShuffle(N0, SrcOpcode) &&
40584 SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0));
40586 SDValue Op01 = peekThroughOneUseBitcasts(N0.getOperand(1));
40606 EVT OpVT = N0.getValueType();
40614 N0.getValueType() == N1.getValueType() &&
40615 IsSafeToMoveShuffle(N0, SrcOpcode) &&
40617 SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0));
40627 EVT OpVT = N0.getValueType();
40939 SDValue N0 = N.getOperand(0);
40943 if (N0.hasOneUse() && ISD::isNormalLoad(N0.getNode())) {
40944 auto *LN = cast<LoadSDNode>(N0);
40957 if (N0.hasOneUse() && N0.getOpcode() == X86ISD::VBROADCAST_LOAD) {
40958 auto *LN = cast<MemSDNode>(N0);
40975 if (N0.hasOneUse() && N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
40976 N0.getOperand(0).hasOneUse() &&
40977 N0.getOperand(0).getValueType() == MVT::i64) {
40978 SDValue In = N0.getOperand(0);
40992 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
40993 if (auto *C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
40995 EVT ScalarVT = N0.getOperand(0).getValueType();
41017 if (!DCI.isBeforeLegalizeOps() && N0.hasOneUse()) {
41018 SDValue V = peekThroughOneUseBitcasts(N0);
41037 SDValue N0 = N.getOperand(0);
41041 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) {
41044 if (N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
41045 MVT SrcVT = N0.getOperand(0).getSimpleValueType();
41053 VT, DAG.getNode(X86ISD::BLENDI, DL, SrcVT, N0.getOperand(0),
41063 if (N0.hasOneUse() && N1.hasOneUse()) {
41066 SDValue LHS = peekThroughOneUseBitcasts(N0);
41133 SDValue N0 = N.getOperand(0);
41136 if (N0.getOpcode() == ISD::BITCAST &&
41137 N0.getOperand(0).getScalarValueSizeInBits() == EltSizeInBits) {
41138 SDValue Src = N0.getOperand(0);
41223 SDValue N0 = N.getOperand(0);
41225 if (N0->hasOneUse()) {
41226 SDValue V = peekThroughOneUseBitcasts(N0);
41256 SDValue N0 = N.getOperand(0);
41260 // MOVS*(N0, OP(N0, N1)) --> MOVS*(N0, SCALAR_TO_VECTOR(OP(N0[0], N1[0])))
41261 // If commutable, allow OP(N1[0], N0[0]).
41267 if (N10 == N0 ||
41268 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) {
41269 if (N10 != N0)
41277 return DAG.getNode(Opcode, DL, VT, N0, SclVec);
41695 SDValue N0 = N->getOperand(0);
41699 if (N0.getOpcode() != ISD::CONCAT_VECTORS ||
41700 N1.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
41701 N1.getNumOperands() != 2 || !N0.getOperand(1).isUndef() ||
41714 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, N0.getOperand(0),
42200 SDValue N0 = Op.getOperand(0);
42207 if (SimplifyDemandedVectorElts(N0, DemandedLHS, LHSUndef, LHSZero, TLO,
42220 SDValue NewN0 = SimplifyMultipleUseDemandedVectorElts(N0, DemandedLHS,
42225 NewN0 = NewN0 ? NewN0 : N0;
42237 SDValue N0 = Op.getOperand(0);
42244 if (SimplifyDemandedVectorElts(N0, DemandedLHS, LHSUndef, LHSZero, TLO,
42256 if (N0 != N1 && !DemandedElts.isAllOnes()) {
42257 SDValue NewN0 = SimplifyMultipleUseDemandedVectorElts(N0, DemandedLHS,
42262 NewN0 = NewN0 ? NewN0 : N0;
43804 if (SDValue N0 = combineBitcastToBoolVector(NewSrcVT, Src, DL, DAG,
43806 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, N0,
43817 if (SDValue N0 = combineBitcastToBoolVector(NewSrcVT, Src, DL, DAG,
43822 N0, DAG.getIntPtrConstant(0, DL));
43829 if (SDValue N0 = combineBitcastToBoolVector(VT, V.getOperand(0), DL, DAG,
43833 return DAG.getNode(Opc, DL, VT, N0, N1);
43844 if (SDValue N0 = combineBitcastToBoolVector(VT, Src0, DL, DAG, Subtarget,
43847 X86ISD::KSHIFTL, DL, VT, N0,
43864 SDValue N0 = N->getOperand(0);
43866 EVT SrcVT = N0.getValueType();
43877 if (SDValue V = combineBitcastvxi1(DAG, VT, N0, dl, Subtarget))
43884 N0 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, N0);
43885 N0 = DAG.getBitcast(MVT::v8i1, N0);
43886 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, N0,
43901 if (N0.getOpcode() == ISD::CONCAT_VECTORS) {
43902 SDValue LastOp = N0.getOperand(N0.getNumOperands() - 1);
43906 SmallVector<SDValue, 4> Ops(N0->op_begin(), N0->op_end());
43908 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
43909 N0 = DAG.getBitcast(MVT::i8, N0);
43910 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
43916 Ops[0] = N0;
43917 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
43918 N0 = DAG.getBitcast(MVT::i8, N0);
43919 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
43927 combineBitcastToBoolVector(VT, N0, SDLoc(N), DAG, Subtarget))
43938 !Subtarget.hasDQI() && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
43939 N0.getOperand(0).getValueType() == MVT::v16i1 &&
43940 isNullConstant(N0.getOperand(1)))
43942 DAG.getBitcast(MVT::i16, N0.getOperand(0)));
43947 if (N0.getOpcode() == X86ISD::VBROADCAST_LOAD && N0.hasOneUse() &&
43949 auto *BCast = cast<MemIntrinsicSDNode>(N0);
43977 if (getTargetConstantBitsFromNode(N0, 64, UndefElts, EltBits,
43980 SDLoc DL(N0);
43992 if (N0.getOpcode() == ISD::BUILD_VECTOR &&
43994 N0.getOperand(0).getValueType() == SrcVT.getScalarType()) {
43997 SDValue Op = N0.getOperand(i);
44002 SDValue N00 = N0.getOperand(0);
44013 if (N0.getOpcode() == ISD::BUILD_VECTOR &&
44016 return createMMXBuildVector(cast<BuildVectorSDNode>(N0), DAG, Subtarget);
44019 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
44020 N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) &&
44021 isNullConstant(N0.getOperand(1))) {
44022 SDValue N00 = N0.getOperand(0);
44029 if (SrcVT == MVT::v2i32 && N0.getOpcode() == ISD::FP_TO_SINT) {
44030 SDLoc DL(N0);
44031 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
44042 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
44043 return combinevXi1ConstantToInteger(N0, DAG);
44048 if (auto *C = dyn_cast<ConstantSDNode>(N0)) {
44050 return DAG.getConstant(1, SDLoc(N0), VT);
44052 return DAG.getConstant(0, SDLoc(N0), VT);
44063 SDValue Src = N0;
44066 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse())
44067 Src = N0.getOperand(0);
44108 switch (N0.getOpcode()) {
44125 SDValue LogicOp0 = N0.getOperand(0);
44126 SDValue LogicOp1 = N0.getOperand(1);
44127 SDLoc DL0(N0);
44130 if (N0.hasOneUse() && LogicOp0.getOpcode() == ISD::BITCAST &&
44135 unsigned Opcode = VT.isFloatingPoint() ? FPOpcode : N0.getOpcode();
44139 if (N0.hasOneUse() && LogicOp1.getOpcode() == ISD::BITCAST &&
44144 unsigned Opcode = VT.isFloatingPoint() ? FPOpcode : N0.getOpcode();
45359 unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N0, SelectionDAG &DAG,
45370 EVT InSVT = N0.getValueType().getScalarType();
45379 if (InSVT != MVT::i1 || N0.getOpcode() != ISD::BITCAST)
45382 SDValue N00 = N0.getOperand(0);
47572 SDValue N0 = N->getOperand(0);
47582 SDValue NewN0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N0);
47736 SDValue N0 = N->getOperand(0);
47742 (((N0.getOpcode() == ISD::ZERO_EXTEND &&
47743 N0.getOperand(0).getScalarValueSizeInBits() <= 8) &&
47746 ((N0.getOpcode() == ISD::SIGN_EXTEND &&
47747 N0.getOperand(0).getScalarValueSizeInBits() <= 8) &&
47755 (N0.getOpcode() == ISD::SIGN_EXTEND &&
47756 N0.getOperand(0).getValueSizeInBits() > 128) &&
47763 DAG.ComputeMaxSignificantBits(N0) > 16)
47803 SDValue ZeroN0 = GetZeroableOp(N0);
47807 N0 = ZeroN0 ? ZeroN0 : N0;
47819 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMADDWDBuilder);
47835 SDValue N0 = N->getOperand(0);
47840 if (Subtarget.hasSSE41() && DAG.ComputeNumSignBits(N0) > 32 &&
47846 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMULDQBuilder,
47852 if (DAG.MaskedValueIsZero(N0, Mask) && DAG.MaskedValueIsZero(N1, Mask)) {
47857 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMULUDQBuilder,
48104 SDValue N0 = N->getOperand(0);
48107 EVT VT = N0.getValueType();
48113 if (N0.getOpcode() == ISD::VSELECT &&
48115 SDValue Cond = N0.getOperand(0);
48116 SDValue N00 = N0.getOperand(1);
48117 SDValue N01 = N0.getOperand(2);
48135 N1C && N0.getOpcode() == ISD::AND &&
48136 N0.getOperand(1).getOpcode() == ISD::Constant) {
48137 SDValue N00 = N0.getOperand(0);
48138 APInt Mask = N0.getConstantOperandAPInt(1);
48172 SDValue N0 = N->getOperand(0);
48174 EVT VT = N0.getValueType();
48186 return DAG.getNode(X86ISD::VSRAV, DL, VT, N0, ShrAmtVal);
48204 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
48205 N0.getOperand(1).getOpcode() != ISD::Constant)
48208 SDValue N00 = N0.getOperand(0);
48209 SDValue N01 = N0.getOperand(1);
48241 SDValue N0 = N->getOperand(0);
48243 EVT VT = N0.getValueType();
48252 if (N0.getOpcode() == ISD::VSELECT &&
48254 SDValue Cond = N0.getOperand(0);
48255 SDValue N00 = N0.getOperand(1);
48256 SDValue N01 = N0.getOperand(2);
48280 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
48284 auto *AndC = dyn_cast<ConstantSDNode>(N0.getOperand(1));
48307 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
48320 SDValue N0 = N->getOperand(0);
48322 EVT SrcVT = N0.getValueType();
48325 N->isOnlyUserOf(N0.getNode()) ? peekThroughOneUseBitcasts(N0) : N0;
48465 SDValue N0 = N->getOperand(0);
48470 assert(N0.getScalarValueSizeInBits() == SrcBitsPerElt &&
48479 if ((N0.isUndef() || N->isOnlyUserOf(N0.getNode())) &&
48481 getTargetConstantBitsFromNode(N0, SrcBitsPerElt, UndefElts0, EltBits0,
48537 (N0.isUndef() || DAG.ComputeNumSignBits(N0) == SrcBitsPerElt) &&
48539 SDValue Not0 = N0.isUndef() ? N0 : IsNOT(N0, DAG);
48543 MVT SrcVT = N0.getSimpleValueType();
48554 N0.getOpcode() == ISD::TRUNCATE && N1.isUndef() && VT == MVT::v16i8 &&
48555 N0.getOperand(0).getValueType() == MVT::v8i32) {
48556 if ((IsSigned && DAG.ComputeNumSignBits(N0) > 8) ||
48558 DAG.MaskedValueIsZero(N0, APInt::getHighBitsSet(16, 8)))) {
48560 return DAG.getNode(X86ISD::VTRUNC, SDLoc(N), VT, N0.getOperand(0));
48565 N0.getOperand(0), DAG.getUNDEF(MVT::v8i32));
48574 if (N0.getOpcode() == ExtOpc &&
48575 N0.getOperand(0).getValueType().is64BitVector() &&
48576 N0.getOperand(0).getScalarValueSizeInBits() == DstBitsPerElt) {
48577 Src0 = N0.getOperand(0);
48584 if ((Src0 || N0.isUndef()) && (Src1 || N1.isUndef())) {
48594 if (N0.getOpcode() == VecInRegOpc && N1.isUndef() &&
48595 N0.getOperand(0).getScalarValueSizeInBits() < DstBitsPerElt)
48596 return getEXTEND_VECTOR_INREG(ExtOpc, SDLoc(N), VT, N0.getOperand(0),
48663 SDValue N0 = N->getOperand(0);
48667 if (ISD::isBuildVectorAllZeros(N0.getNode()))
48677 return getTargetVShiftByConstNode(X86Opc, SDLoc(N), VT.getSimpleVT(), N0,
48698 SDValue N0 = N->getOperand(0);
48701 assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 &&
48706 if (N0.isUndef())
48720 return N0;
48723 if (ISD::isBuildVectorAllZeros(N0.getNode()))
48724 // N0 is all zeros or undef. We guarantee that the bits shifted into the
48729 if (!LogicalShift && ISD::isBuildVectorAllOnes(N0.getNode()))
48730 // N0 is all ones or undef. We guarantee that the bits shifted into the
48743 return DAG.getNode(Opcode, SDLoc(N), VT, N0.getOperand(0),
48748 if (Opcode == N0.getOpcode())
48749 return MergeShifts(N0.getOperand(0), ShiftVal, N0.getConstantOperandVal(1));
48752 if (Opcode == X86ISD::VSHLI && N0.getOpcode() == ISD::ADD &&
48753 N0.getOperand(0) == N0.getOperand(1))
48754 return MergeShifts(N0.getOperand(0), ShiftVal, 1);
48768 N0.getOpcode() == X86ISD::PSHUFD &&
48769 N0.getConstantOperandVal(1) == getV4X86ShuffleImm({1, 1, 3, 3}) &&
48770 N0->hasOneUse()) {
48771 SDValue BC = peekThroughOneUseBitcasts(N0.getOperand(0));
48815 if (N->isOnlyUserOf(N0.getNode())) {
48816 if (SDValue C = TryConstantFold(N0))
48821 SDValue BC = peekThroughOneUseBitcasts(N0);
48889 SDValue N0 = N->getOperand(0);
48891 SDValue CMP0 = N0.getOperand(1);
48927 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
48996 SDValue N0 = N->getOperand(0);
48999 if (SDValue Not = IsNOT(N0, DAG)) {
49004 Y = N0;
49059 SDValue N0 = N->getOperand(0);
49063 if (SDValue Not = GetNot(N0)) {
49068 Y = N0;
49114 SDValue N0 = N.getOperand(0);
49121 if (SDValue NN0 = PromoteMaskArithmetic(N0, DL, VT, DAG, Depth + 1))
49122 N0 = NN0;
49125 if (N0.getOpcode() != ISD::TRUNCATE)
49129 if (N0.getOperand(0).getValueType() != VT)
49132 N0 = N0.getOperand(0);
49150 return DAG.getNode(N.getOpcode(), DL, VT, N0, N1);
49207 SDValue N0 = N->getOperand(0);
49211 if (!((N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) ||
49212 (N0.getOpcode() == ISD::SETCC && N1.getOpcode() == ISD::SETCC)))
49215 SDValue N00 = N0.getOperand(0);
49226 if (N0.getOpcode() == ISD::BITCAST && !DCI.isBeforeLegalizeOps()) {
49232 if (VT != MVT::i1 || N0.getOpcode() != ISD::SETCC || !N0.hasOneUse() ||
49236 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0.getOperand(2))->get();
49253 SDValue N01 = N0.getOperand(1);
49272 SDValue N0 = N->getOperand(0);
49276 if (N0.getOpcode() != X86ISD::MOVMSK || !N0.hasOneUse() ||
49280 SDValue Vec0 = N0.getOperand(0);
49307 SDValue N0 = N->getOperand(0);
49312 if (!N0.hasOneUse() || !N1.hasOneUse())
49316 SDValue BC0 = peekThroughOneUseBitcasts(N0);
49350 SDValue N0 = N->getOperand(0);
49355 if (!N0.hasOneUse() || !N1.hasOneUse())
49359 N0 = peekThroughOneUseBitcasts(N0);
49362 if (N0.getOpcode() != X86ISD::PACKSS || N1.getOpcode() != X86ISD::PACKSS)
49365 MVT DstVT = N0.getSimpleValueType();
49369 MVT SrcVT = N0.getOperand(0).getSimpleValueType();
49373 if (DAG.ComputeNumSignBits(N0.getOperand(0)) != NumSrcBits ||
49374 DAG.ComputeNumSignBits(N0.getOperand(1)) != NumSrcBits ||
49380 SDValue LHS = DAG.getNode(Opc, DL, SrcVT, N0.getOperand(0), N1.getOperand(0));
49381 SDValue RHS = DAG.getNode(Opc, DL, SrcVT, N0.getOperand(1), N1.getOperand(1));
49854 SDValue N0 = N->getOperand(0);
49864 DAG.getBitcast(MVT::v4f32, N0),
49872 DAG.MaskedValueIsZero(N0, HiMask)) {
49873 SDValue LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, N0);
49909 if (N0.getOpcode() == ISD::MUL && N0.hasOneUse()) {
49915 isConstOrConstSplat(N0.getOperand(1), /*AllowUndefs*/ true,
49923 SDValue Neg = DAG.getNegative(N0.getOperand(0), dl, VT);
49974 unsigned Opc0 = N0.getOpcode();
49976 getTargetConstantFromNode(N0.getOperand(1)) &&
49978 N0->hasOneUse() && N0.getOperand(1)->hasOneUse()) {
49979 SDValue MaskMul = DAG.getNode(ISD::AND, dl, VT, N0.getOperand(1), N1);
49980 return DAG.getNode(Opc0, dl, VT, N0.getOperand(0), MaskMul);
49986 if (isOneConstant(N1) && N0->hasOneUse()) {
49987 SDValue Src = N0;
50053 std::tie(Bits1, Elts1) = GetDemandedMasks(N0);
50055 if (TLI.SimplifyDemandedVectorElts(N0, Elts0, DCI) ||
50057 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) ||
50064 SDValue NewN0 = TLI.SimplifyMultipleUseDemandedBits(N0, Bits0, Elts0, DAG);
50067 return DAG.getNode(ISD::AND, dl, VT, NewN0 ? NewN0 : N0,
50073 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
50074 isa<ConstantSDNode>(N0.getOperand(1)) && N0->hasOneUse()) {
50076 SDValue SrcVec = N0.getOperand(0);
50082 if (VT == SrcVecVT.getScalarType() && N0->isOnlyUserOf(SrcVec.getNode()) &&
50089 unsigned Idx = N0.getConstantOperandVal(1);
50106 N0.getOperand(1));
50126 SDValue N0 = peekThroughBitcasts(N->getOperand(0));
50128 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
50134 !N0.getOperand(1).hasOneUse() || !N1.getOperand(1).hasOneUse()))
50140 if (!getTargetConstantBitsFromNode(N0.getOperand(1), 8, UndefElts0, EltBits0,
50165 SDValue A = DAG.getBitcast(OpVT, N0.getOperand(1));
50166 SDValue B = DAG.getBitcast(OpVT, N0.getOperand(0));
50176 DAG.getNode(X86ISD::ANDNP, DL, VT, DAG.getBitcast(VT, N0.getOperand(1)),
50186 SDValue N0 = N->getOperand(0);
50191 std::swap(N0, N1);
50194 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != X86ISD::ANDNP)
50201 if (N0.getOperand(0) == Mask)
50202 Y = N0.getOperand(1);
50203 else if (N0.getOperand(1) == Mask)
50204 Y = N0.getOperand(0);
50402 SDValue N0 = Node->getOperand(0);
50403 if (N0->getOpcode() != ISD::AND || !N0->hasOneUse())
50410 SDValue N00 = N0->getOperand(0);
50411 SDValue N01 = N0->getOperand(1);
50633 static SDValue combineOrXorWithSETCC(SDNode *N, SDValue N0, SDValue N1,
50644 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
50645 N0.getOperand(0).getOpcode() == X86ISD::SETCC && N0.hasOneUse()) {
50652 if (SDValue R = combineAddOrSubToADCOrSBB(IsSub, DL, VT, N1, N0, DAG))
50659 if (N->getOpcode() == ISD::XOR && N0.getOpcode() == X86ISD::PCMPEQ &&
50660 N0.getOperand(0).getOpcode() == ISD::AND &&
50661 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode()) &&
50666 if (getTargetConstantBitsFromNode(N0.getOperand(0).getOperand(1),
50674 return DAG.getNode(X86ISD::PCMPEQ, SDLoc(N), VT, N0.getOperand(0),
50675 N0.getOperand(0).getOperand(1));
50685 SDValue N0 = N->getOperand(0);
50695 DAG.getBitcast(MVT::v4f32, N0),
50751 N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
50752 isNullConstant(N0.getOperand(0))) {
50753 SDValue Cond = N0.getOperand(1);
50778 if (N0.getOpcode() == X86ISD::KSHIFTL || N1.getOpcode() == X86ISD::KSHIFTL) {
50784 DAG.MaskedVectorIsZero(N0, UpperElts)) {
50787 extractSubVector(N0, 0, DAG, dl, HalfElts),
50790 if (NumElts >= 16 && N0.getOpcode() == X86ISD::KSHIFTL &&
50791 N0.getConstantOperandAPInt(1) == HalfElts &&
50796 extractSubVector(N0.getOperand(0), 0, DAG, dl, HalfElts));
50823 if (SimplifyUndemandedElts(N0, N1) || SimplifyUndemandedElts(N1, N0)) {
50835 if (SDValue R = combineOrXorWithSETCC(N, N0, N1, DAG))
50851 SDValue N0 = N->getOperand(0);
50855 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
50863 SDValue Shift = N0.getOperand(0);
51932 auto GetShuffle = [&](SDValue Op, SDValue &N0, SDValue &N1,
51951 N0 = !SrcOps.empty() ? SrcOps[0] : SDValue();
51957 std::tie(N0, N1) = DAG.SplitVector(SrcOps[0], SDLoc(Op));
52347 auto TruncateArithmetic = [&](SDValue N0, SDValue N1) {
52348 SDValue Trunc0 = DAG.getNode(ISD::TRUNCATE, DL, VT, N0);
52499 SDValue N0 = SSatVal.getOperand(0);
52502 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
52505 SDValue N00 = N0.getOperand(0);
52506 SDValue N01 = N0.getOperand(1);
52579 // N0 indices be the even element. N1 indices must be the next odd element.
52997 SDValue N0 = N->getOperand(0);
53000 if (N0.getOpcode() != ISD::CTLZ_ZERO_UNDEF &&
53009 OpSizeTM1 = N0;
53013 OpCTLZ = N0;
53044 SDValue N0 = N->getOperand(0);
53053 DAG.getBitcast(MVT::v4f32, N0),
53081 if (SDValue R = combineOrXorWithSETCC(N, N0, N1, DAG))
53089 if (llvm::isAllOnesConstant(N1) && N0.getOpcode() == ISD::BITCAST &&
53090 N0.getOperand(0).getValueType().isVector() &&
53091 N0.getOperand(0).getValueType().getVectorElementType() == MVT::i1 &&
53092 TLI.isTypeLegal(N0.getOperand(0).getValueType()) && N0.hasOneUse()) {
53094 VT, DAG.getNOT(DL, N0.getOperand(0), N0.getOperand(0).getValueType()));
53101 N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.getOperand(0).isUndef() &&
53102 TLI.isTypeLegal(N0.getOperand(1).getValueType())) {
53104 ISD::INSERT_SUBVECTOR, DL, VT, N0.getOperand(0),
53105 DAG.getNOT(DL, N0.getOperand(1), N0.getOperand(1).getValueType()),
53106 N0.getOperand(2));
53112 if ((N0.getOpcode() == ISD::TRUNCATE || N0.getOpcode() == ISD::ZERO_EXTEND) &&
53113 N0.getOperand(0).getOpcode() == N->getOpcode()) {
53114 SDValue TruncExtSrc = N0.getOperand(0);
53134 SDValue N0 = N->getOperand(0);
53138 if (VT.isInteger() && N0.getOpcode() == ISD::BITCAST && N0.hasOneUse()) {
53139 SDValue Src = N0.getOperand(0);
53163 SDValue N0 = N->getOperand(0);
53174 N0 = DAG.getNode(ISD::XOR, DL, VT, N0, SignMask);
53177 DAG.getNode(ISD::AVGCEILU, DL, VT, N0, N1), SignMask);
53223 SDValue N0 = N->getOperand(0);
53242 if (N0.getOpcode() == X86ISD::FXOR && isAllOnesConstantFP(N0.getOperand(1)))
53243 return DAG.getNode(X86ISD::FANDN, DL, VT, N0.getOperand(0), N1);
53247 return DAG.getNode(X86ISD::FANDN, DL, VT, N1.getOperand(0), N0);
53464 SDValue N0 = N->getOperand(0);
53473 if (N0.isUndef() || N1.isUndef())
53477 if (ISD::isBuildVectorAllZeros(N0.getNode()))
53486 return DAG.getNOT(DL, N0, VT);
53489 if (SDValue Not = IsNOT(N0, DAG))
53497 DL, DAG.getNode(ISD::OR, DL, VT, N0, DAG.getBitcast(VT, Not)), VT);
53502 if (getTargetConstantBitsFromNode(N0, EltSizeInBits, Undefs0, EltBits0,
53514 // Constant fold NOT(N0) to allow us to use AND.
53517 if (N0->hasOneUse()) {
53518 SDValue BC0 = peekThroughOneUseBitcasts(N0);
53563 std::tie(Bits1, Elts1) = GetDemandedMasks(N0, true);
53566 if (TLI.SimplifyDemandedVectorElts(N0, Elts0, DCI) ||
53568 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) ||
53641 SDValue N0 = N->getOperand(0);
53650 if ((N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
53651 N0.hasOneUse()) {
53652 IntermediateBitwidthOp = N0;
53653 N0 = N0.getOperand(0);
53657 if (N0.getOpcode() != X86ISD::CMOV || !N0.hasOneUse())
53660 SDValue CMovOp0 = N0.getOperand(0);
53661 SDValue CMovOp1 = N0.getOperand(1);
53689 N0.getOperand(2), N0.getOperand(3));
53705 SDValue N0 = N->getOperand(0);
53715 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
53716 N0.getOpcode() == ISD::SIGN_EXTEND)) {
53717 SDValue N00 = N0.getOperand(0);
53727 if (SDValue Promote = PromoteMaskArithmetic(N0, dl, DAG, Subtarget))
53868 SDValue N0 = N->getOperand(0);
53873 if (!Subtarget.hasAVX512() || !VT.isVector() || N0.getOpcode() != ISD::SETCC)
53883 if (N0.getOperand(0).getValueType().getVectorElementType() == MVT::f16)
53892 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
53897 EVT N00VT = N0.getOperand(0).getValueType();
53902 SDValue Res = DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
53905 Res = DAG.getZeroExtendInReg(Res, dl, N0.getValueType());
53913 SDValue N0 = N->getOperand(0);
53919 N0.getOpcode() == X86ISD::SETCC_CARRY) {
53920 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, N0->getOperand(0),
53921 N0->getOperand(1));
53922 bool ReplaceOtherUses = !N0.hasOneUse();
53926 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
53927 N0.getValueType(), Setcc);
53928 DCI.CombineTo(N0.getNode(), Trunc);
53943 if (SDValue V = combineToExtendBoolVectorInReg(N->getOpcode(), DL, VT, N0,
53951 if (N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG)
53952 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
54129 SDValue N0 = N->getOperand(0);
54135 N0.getOpcode() == X86ISD::SETCC_CARRY) {
54136 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, N0->getOperand(0),
54137 N0->getOperand(1));
54138 bool ReplaceOtherUses = !N0.hasOneUse();
54142 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
54143 N0.getValueType(), Setcc);
54144 DCI.CombineTo(N0.getNode(), Trunc);
54157 if (SDValue V = combineToExtendBoolVectorInReg(N->getOpcode(), dl, VT, N0,
54172 if (N0.getOpcode() == X86ISD::PACKUS && N0.getValueSizeInBits() == 128 &&
54173 VT.getScalarSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits()) {
54174 SDValue N00 = N0.getOperand(0);
54175 SDValue N01 = N0.getOperand(1);
54229 auto MatchOrCmpEq = [&](SDValue N0, SDValue N1) {
54230 if (N0.getOpcode() == ISD::OR && N0->hasOneUse()) {
54231 if (N0.getOperand(0) == N1)
54233 N0.getOperand(1));
54234 if (N0.getOperand(1) == N1)
54236 N0.getOperand(0));
54247 auto MatchAndCmpEq = [&](SDValue N0, SDValue N1) {
54248 if (N0.getOpcode() == ISD::AND && N0->hasOneUse()) {
54249 if (N0.getOperand(0) == N1)
54251 DAG.getNOT(DL, N0.getOperand(1), OpVT));
54252 if (N0.getOperand(1) == N1)
54254 DAG.getNOT(DL, N0.getOperand(0), OpVT));
55319 auto MatchGeneric = [&](SDValue N0, SDValue N1, bool Negate) {
55320 SDValue Ops[] = {N0, N1};
55509 SDValue N0 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Mul.getOperand(0));
55520 return SplitOpsAndApply(DAG, Subtarget, DL, VT, { N0, N1 }, PMADDBuilder);
55526 static SDValue matchPMADDWD_2(SelectionDAG &DAG, SDValue N0, SDValue N1,
55532 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL)
55540 SDValue N00 = N0.getOperand(0);
55541 SDValue N01 = N0.getOperand(1);
55605 // N0 indices be the even element. N1 indices must be the next odd element.
55666 static SDValue combineAddOfPMADDWD(SelectionDAG &DAG, SDValue N0, SDValue N1,
55668 if (N0.getOpcode() != N1.getOpcode() || N0.getOpcode() != X86ISD::VPMADDWD)
55676 MVT OpVT = N0.getOperand(0).getSimpleValueType();
55681 DAG.MaskedValueIsZero(N0.getOperand(0), DemandedBits, DemandedHiElts) ||
55682 DAG.MaskedValueIsZero(N0.getOperand(1), DemandedBits, DemandedHiElts);
55700 DAG.getVectorShuffle(OpVT, DL, N0.getOperand(0), N1.getOperand(0), Mask);
55702 DAG.getVectorShuffle(OpVT, DL, N0.getOperand(1), N1.getOperand(1), Mask);
55849 SDValue N0 = N->getOperand(0);
55882 return DAG.getNode(ISD::ADD, DL, VT, N0, Cmov);
58088 SDValue N0 = Op.getOperand(0);
58090 if (X86::mayFoldLoad(N0, Subtarget) && IsFoldableRMW(N0, Op))
58102 SDValue N0 = Op.getOperand(0);
58106 (!Commute || !isa<ConstantSDNode>(N0) ||
58109 if (X86::mayFoldLoad(N0, Subtarget) &&
58111 (Op.getOpcode() != ISD::MUL && IsFoldableRMW(N0, Op))))
58113 if (IsFoldableAtomicRMW(N0, Op) ||