Lines Matching defs:KnownUndef
5550 APInt &KnownUndef, APInt &KnownZero) {
5552 KnownUndef = KnownZero = APInt::getZero(Size);
5568 KnownUndef.setBit(i);
5590 KnownUndef.setBit(i);
5619 KnownUndef.setBit(i);
5633 APInt &KnownUndef, APInt &KnownZero) {
5645 KnownUndef = KnownZero = APInt::getZero(Size);
5672 KnownUndef.setBit(i);
5685 KnownUndef.setBit(i);
5698 KnownUndef.setBit(i);
5713 KnownUndef.setBit(i);
5721 KnownUndef.setBit(i);
5734 const APInt &KnownUndef,
5738 assert(KnownUndef.getBitWidth() == NumElts &&
5742 if (KnownUndef[i])
5751 APInt &KnownUndef,
5754 KnownUndef = KnownZero = APInt::getZero(NumElts);
5759 KnownUndef.setBit(i);
6324 APInt &KnownUndef, APInt &KnownZero,
6334 if (getTargetShuffleAndZeroables(Op, Mask, Inputs, KnownUndef, KnownZero)) {
6336 resolveTargetShuffleFromZeroables(Mask, KnownUndef, KnownZero);
6341 resolveZeroablesFromTargetShuffle(Mask, KnownUndef, KnownZero);
6352 APInt KnownUndef, KnownZero;
6353 return getTargetShuffleInputs(Op, DemandedElts, Inputs, Mask, KnownUndef,
17663 APInt KnownUndef, KnownZero;
17664 computeZeroableShuffleElements(OrigMask, V1, V2, KnownUndef, KnownZero);
17666 APInt Zeroable = KnownUndef | KnownZero;
38774 APInt KnownUndef, KnownZero;
38775 resolveZeroablesFromTargetShuffle(Mask, KnownUndef, KnownZero);
38776 APInt Zeroable = KnownUndef | KnownZero;
41883 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
42076 if (SimplifyDemandedVectorElts(Src, DemandedSrc, KnownUndef, KnownZero, TLO,
42080 KnownUndef <<= ShiftAmt;
42115 if (SimplifyDemandedVectorElts(Src, DemandedSrc, KnownUndef, KnownZero, TLO,
42119 KnownUndef.lshrInPlace(ShiftAmt);
42281 KnownUndef = SrcUndef.zextOrTrunc(NumElts);
42311 KnownUndef = LHSUndef & RHSUndef;
42579 KnownUndef = OpUndef;
42588 KnownUndef.setAllBits();
42891 APInt KnownUndef, KnownZero;
42893 if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
43022 APInt KnownUndef, KnownZero;
43024 if (SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, KnownZero,