Lines Matching defs:IsROTL

30161   bool IsROTL = Opcode == ISD::ROTL;
30177       unsigned RotOpc = IsROTL ? X86ISD::VROTLI : X86ISD::VROTRI;
30189     unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR;
30195   if (!IsROTL) {
30224     assert(IsROTL && "Only ROTL expected");
30243     uint64_t ShlAmt = IsROTL ? RotAmt : (EltSizeInBits - RotAmt);
30244     uint64_t SrlAmt = IsROTL ? (EltSizeInBits - RotAmt) : RotAmt;
30276         unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR;
30279       unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI;
30286       return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL);
30291   unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL;
30306     return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL);
30331       if (IsROTL)
30356     if (!IsROTL && !useVPTERNLOG(Subtarget, VT)) {
30358       IsROTL = true;
30361     unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL;
30362     unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL;
30410     SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt);
30411     SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR);
30416   if (!IsROTL) {
30418     IsROTL = true;
30424   assert(IsROTL && "Only ROTL supported");