Lines Matching defs:IdxVal
3914 static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
3928 IdxVal &= ~(ElemsPerChunk - 1);
3933 Vec->ops().slice(IdxVal, ElemsPerChunk));
3937 Vec.getOperand(1).getValueType().getVectorNumElements() <= IdxVal &&
3941 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
3951 static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
3955 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
3959 static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
3962 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
3965 static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
3983 IdxVal &= ~(ElemsPerChunk - 1);
3985 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
3995 static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
3998 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4332 unsigned IdxVal = Op.getConstantOperandVal(2);
4338 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4350 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) {
4360 assert(IdxVal + SubVecNumElems <= NumElems &&
4361 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4366 if (IdxVal == 0) {
4385 assert(IdxVal != 0 && "Unexpected index");
4387 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
4392 assert(IdxVal != 0 && "Unexpected index");
4394 if (llvm::all_of(Vec->ops().slice(IdxVal + SubVecNumElems),
4397 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
4401 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4412 if (IdxVal + SubVecNumElems == NumElems) {
4414 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
4427 SDValue ShiftBits = DAG.getTargetConstant(NumElems - IdxVal, dl, MVT::i8);
4443 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4447 APInt Mask0 = APInt::getBitsSet(NumElems, IdxVal, IdxVal + SubVecNumElems);
4469 unsigned LowShift = NumElems - IdxVal;
4476 unsigned HighShift = IdxVal + SubVecNumElems;
17901 // If IdxVal is 0, it's cheaper to do a move instead of a pextrb, unless
17909 unsigned IdxVal = Idx->getAsZExtVal();
17911 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
17971 unsigned IdxVal = IdxC->getZExtValue();
17972 if (IdxVal == 0) // the operation is legal
17980 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
18066 unsigned IdxVal = IdxC->getZExtValue();
18072 Vec = extract128BitVector(Vec, IdxVal, DAG, dl);
18078 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
18080 IdxVal &= ElemsPerChunk - 1;
18082 DAG.getIntPtrConstant(IdxVal, dl));
18090 // If IdxVal is 0, it's cheaper to do a move instead of a pextrw, unless
18092 if (IdxVal == 0 && !X86::mayFoldIntoZeroExtend(Op) &&
18103 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
18119 int DWordIdx = IdxVal / 4;
18124 int ShiftVal = (IdxVal % 4) * 8;
18131 int WordIdx = IdxVal / 2;
18136 int ShiftVal = (IdxVal % 2) * 8;
18145 if (IdxVal == 0)
18150 Mask[0] = static_cast<int>(IdxVal);
18160 if (IdxVal == 0)
18256 uint64_t IdxVal = N2C->getZExtValue();
18270 CstVectorElts[IdxVal] = OnesCst;
18280 BlendMask.push_back(i == IdxVal ? i + NumElts : i);
18292 if (VT.is256BitVector() && IdxVal == 0) {
18311 if (IdxVal >= NumEltsIn128 &&
18318 BlendMask.push_back(i == IdxVal ? i + NumElts : i);
18323 SDValue V = extract128BitVector(N0, IdxVal, DAG, dl);
18327 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
18333 return insert128BitVector(N0, V, IdxVal, DAG, dl);
18338 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(N0.getNode())) {
18371 N2 = DAG.getTargetConstant(IdxVal, dl, MVT::i8);
18387 if (IdxVal == 0 && (!MinSize || !X86::mayFoldLoad(N1, Subtarget))) {
18402 DAG.getTargetConstant(IdxVal << 4, dl, MVT::i8));
18466 uint64_t IdxVal = Op.getConstantOperandVal(1);
18468 if (IdxVal == 0) // the operation is legal
18476 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
56790 uint64_t IdxVal = N->getConstantOperandVal(2);
56810 DAG.getIntPtrConstant(IdxVal + Idx2Val, dl));
56817 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 &&
56849 (IdxVal != 0 ||
56861 Mask[i + IdxVal] = i + ExtIdxVal + VecNumElts;
56896 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST)
56901 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() &&
56916 if (IdxVal == (OpVT.getVectorNumElements() / 2) && SubVec.hasOneUse() &&
57005 unsigned IdxVal = N->getConstantOperandVal(1);
57049 return DAG.getBuildVector(VT, DL, InVec->ops().slice(IdxVal, NumSubElts));
57057 IdxVal == InVec.getConstantOperandVal(2) &&
57061 unsigned NewIdxVal = InVec.getConstantOperandVal(2) - IdxVal;
57070 if (IdxVal != 0 && (InVec.getOpcode() == X86ISD::VBROADCAST ||
57076 if (IdxVal != 0 && InVec.getOpcode() == X86ISD::SUBV_BROADCAST_LOAD &&
57081 if ((InSizeInBits % SizeInBits) == 0 && (IdxVal % NumSubElts) == 0) {
57089 unsigned SubVecIdx = IdxVal / NumSubElts;
57117 if (IdxVal == 0 && VT == MVT::v2f64 && InVecVT == MVT::v4f64) {
57139 extractSubVector(Src, IdxVal, DAG, DL, SizeInBits));
57141 if (IdxVal == 0 &&
57151 if (IdxVal == 0 && InOpcode == ISD::VSELECT &&
57160 if (IdxVal == 0 && InOpcode == ISD::TRUNCATE && Subtarget.hasVLX() &&
57173 extractSubVector(InVec.getOperand(0), IdxVal, DAG, DL, SizeInBits);
57175 extractSubVector(InVec.getOperand(1), IdxVal, DAG, DL, SizeInBits);
57183 extractSubVector(InVec.getOperand(0), IdxVal, DAG, DL, SizeInBits);
57194 extractSubVector(InVec.getOperand(0), IdxVal, DAG, DL, SizeInBits);