Lines Matching +full:se +full:- +full:pos
1 //====- X86FlagsCopyLowering.cpp - Lowers COPY nodes of EFLAGS ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 /// and other non-status flags being overwritten. Using sequences involving
21 //===----------------------------------------------------------------------===//
62 #define PASS_KEY "x86-flags-copy-lowering"
104 void insertTest(MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos,
107 void rewriteSetCC(MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos,
111 MachineBasicBlock::iterator Pos, const DebugLoc &Loc,
113 void rewriteMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos,
157 assert(!std::prev(PrevI.getIterator())->isTerminator() &&
189 for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI)
247 if (FlagDef->isDead() && X86::getNFVariant(MI.getOpcode()))
259 TII = Subtarget->getInstrInfo();
260 TRI = Subtarget->getRegisterInfo();
267 if (none_of(MRI->def_instructions(X86::EFLAGS), [](const MachineInstr &MI) {
280 MDT = &MDTWrapper->getDomTree();
283 OwnedMDT->getBase().recalculate(MF);
303 // OP1 implicit-def dead $eflags
307 // ->
311 if (Subtarget->hasNF()) {
319 MachineOperand &VOp = CopyI->getOperand(1);
320 MachineInstr *CopyDefI = MRI->getVRegDef(VOp.getReg());
321 MachineBasicBlock *CopyIMBB = CopyI->getParent();
322 MachineBasicBlock *CopyDefIMBB = CopyDefI->getParent();
323 // Walk all basic blocks reachable in depth-first iteration on the inverse
327 // has to be NF-convertible if it clobbers flags.
332 ? MBB->begin()
334 E = (MBB != CopyIMBB) ? MBB->end()
351 CopyI->eraseFromParent();
352 if (MRI->use_nodbg_empty(CopyDefI->getOperand(0).getReg())) {
354 CopyDefI->eraseFromParent();
358 unsigned NewOpc = X86::getNFVariant(Clobber->getOpcode());
360 Clobber->setDesc(TII->get(NewOpc));
361 Clobber->removeOperand(
362 Clobber->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr)
363 ->getOperandNo());
370 BI->addLiveIn(X86::EFLAGS);
382 // OP1 implicit-def dead $eflags
386 // ->
389 // OP1 implicit-def dead $eflags
390 // TEST8rr %1, %1, implicit-def $eflags
393 MachineBasicBlock &MBB = *CopyI->getParent();
395 MachineOperand &VOp = CopyI->getOperand(1);
398 MachineInstr &CopyDefI = *MRI->getVRegDef(VOp.getReg());
424 CopyI->eraseFromParent();
425 if (MRI->use_empty(CopyDefI.getOperand(0).getReg()))
430 MachineOperand &DOp = CopyI->getOperand(0);
440 LLVM_DEBUG(dbgs() << "Rewriting copy: "; CopyI->dump());
442 // Walk up across live-in EFLAGS to find where they were actually def'ed.
466 assert(MDT->dominates(BeginMBB, EndMBB) &&
475 for (auto *PredMBB : MBB->predecessors()) {
478 if (HasEFLAGSClobber(PredMBB->begin(), PredMBB->end()))
487 while (TestMBB->isLiveIn(X86::EFLAGS) && !TestMBB->pred_empty() &&
488 !HasEFLAGSClobber(TestMBB->begin(), TestPos)) {
492 std::accumulate(std::next(TestMBB->pred_begin()), TestMBB->pred_end(),
493 *TestMBB->pred_begin(),
495 return MDT->findNearestCommonDominator(LHS, RHS);
505 if (HasEFLAGSClobber(HoistMBB->getFirstTerminator()->getIterator(),
506 HoistMBB->instr_end()))
511 TestPos = TestMBB->getFirstTerminator()->getIterator();
517 llvm::reverse(llvm::make_range(TestMBB->instr_begin(), TestPos)),
521 if (DefIt.base() != TestMBB->instr_begin()) {
523 DefIt->dump();
525 dbgs() << " Using live-in flags for BB:\n";
526 TestMBB->dump();
565 ? std::next(CopyI->getIterator())
571 // def or the copy itself, break so that we don't re-process any part of
593 if (FlagUse->isKill())
600 // tail calls, as those are not introduced into the X86 MI until post-RA
614 // Otherwise we can just rewrite in-place.
618 MRI->replaceRegWith(MI.getOperand(0).getReg(),
638 // Otherwise we need to scan successors for ones where the flags live-in
641 if (SuccMBB->isLiveIn(X86::EFLAGS) &&
655 // a hard check even in non-debug builds here.
656 if (SuccMBB == TestMBB || !MDT->dominates(TestMBB, SuccMBB)) {
663 TestMBB->dump();
665 SuccMBB->dump();
675 SuccMBB->removeLiveIn(X86::EFLAGS);
686 if (JmpI->getParent() == LastJmpMBB)
687 splitBlock(*JmpI->getParent(), *JmpI, *TII);
689 LastJmpMBB = JmpI->getParent();
714 /// can re-use them rather than adding duplicates.
726 "A non-storing SETcc should always define a register!");
741 Register Reg = MRI->createVirtualRegister(PromoteRC);
742 auto SetI = BuildMI(TestMBB, TestPos, TestLoc, TII->get(X86::SETCCr), Reg)
745 LLVM_DEBUG(dbgs() << " save cond: "; SetI->dump());
765 MachineBasicBlock::iterator Pos,
768 BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
770 LLVM_DEBUG(dbgs() << " test cond: "; TestI->dump());
775 MachineBasicBlock::iterator Pos,
785 CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);
791 "Cannot have a non-register defined operand to SETcc!");
795 MRI->clearKillFlags(OldReg);
796 MRI->replaceRegWith(OldReg, CondReg);
803 TII->get(X86::MOV8mr));
814 MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos,
828 CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);
831 Register TmpReg = MRI->createVirtualRegister(PromoteRC);
834 TII->get(Subtarget->hasNDD() ? X86::ADD8ri_ND : X86::ADD8ri))
839 LLVM_DEBUG(dbgs() << " add cond: "; AddI->dump());
841 MI.findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr)->setIsKill(true);
889 MachineBasicBlock::iterator Pos,
903 getCondOrInverseInReg(MBB, Pos, Loc, CC, CondRegs);
912 MI.setDesc(TII->get(getOpcodeWithCC(MI.getOpcode(), NewCC)));
914 MI.getOperand(MI.getDesc().getNumOperands() - 1).setImm(NewCC);
916 MI.findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr)->setIsKill(true);