Lines Matching defs:Opc
86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
120 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
333 unsigned Opc = 0;
337 Opc = X86::MOV8rm;
340 Opc = X86::MOV16rm;
343 Opc = X86::MOV32rm;
347 Opc = X86::MOV64rm;
350 Opc = HasAVX512 ? X86::VMOVSSZrm_alt
356 Opc = HasAVX512 ? X86::VMOVSDZrm_alt
366 Opc = HasVLX ? X86::VMOVNTDQAZ128rm :
369 Opc = HasVLX ? X86::VMOVAPSZ128rm :
372 Opc = HasVLX ? X86::VMOVUPSZ128rm :
377 Opc = HasVLX ? X86::VMOVNTDQAZ128rm :
380 Opc = HasVLX ? X86::VMOVAPDZ128rm :
383 Opc = HasVLX ? X86::VMOVUPDZ128rm :
391 Opc = HasVLX ? X86::VMOVNTDQAZ128rm :
394 Opc = HasVLX ? X86::VMOVDQA64Z128rm :
397 Opc = HasVLX ? X86::VMOVDQU64Z128rm :
403 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm;
407 Opc = HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm;
409 Opc = HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm;
414 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm;
418 Opc = HasVLX ? X86::VMOVAPDZ256rm : X86::VMOVAPDYrm;
420 Opc = HasVLX ? X86::VMOVUPDZ256rm : X86::VMOVUPDYrm;
428 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm;
432 Opc = HasVLX ? X86::VMOVDQA64Z256rm : X86::VMOVDQAYrm;
434 Opc = HasVLX ? X86::VMOVDQU64Z256rm : X86::VMOVDQUYrm;
439 Opc = X86::VMOVNTDQAZrm;
441 Opc = (Alignment >= 64) ? X86::VMOVAPSZrm : X86::VMOVUPSZrm;
446 Opc = X86::VMOVNTDQAZrm;
448 Opc = (Alignment >= 64) ? X86::VMOVAPDZrm : X86::VMOVUPDZrm;
458 Opc = X86::VMOVNTDQAZrm;
460 Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm;
468 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg);
490 unsigned Opc = 0;
503 case MVT::i8: Opc = X86::MOV8mr; break;
504 case MVT::i16: Opc = X86::MOV16mr; break;
506 Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTImr : X86::MOV32mr;
510 Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTI_64mr : X86::MOV64mr;
515 Opc = X86::MOVNTSS;
517 Opc = HasAVX512 ? X86::VMOVSSZmr :
520 Opc = X86::ST_Fp32m;
525 Opc = X86::MOVNTSD;
527 Opc = HasAVX512 ? X86::VMOVSDZmr :
530 Opc = X86::ST_Fp64m;
533 Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr;
538 Opc = HasVLX ? X86::VMOVNTPSZ128mr :
541 Opc = HasVLX ? X86::VMOVAPSZ128mr :
544 Opc = HasVLX ? X86::VMOVUPSZ128mr :
550 Opc = HasVLX ? X86::VMOVNTPDZ128mr :
553 Opc = HasVLX ? X86::VMOVAPDZ128mr :
556 Opc = HasVLX ? X86::VMOVUPDZ128mr :
565 Opc = HasVLX ? X86::VMOVNTDQZ128mr :
568 Opc = HasVLX ? X86::VMOVDQA64Z128mr :
571 Opc = HasVLX ? X86::VMOVDQU64Z128mr :
578 Opc = HasVLX ? X86::VMOVNTPSZ256mr : X86::VMOVNTPSYmr;
580 Opc = HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr;
582 Opc = HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr;
588 Opc = HasVLX ? X86::VMOVNTPDZ256mr : X86::VMOVNTPDYmr;
590 Opc = HasVLX ? X86::VMOVAPDZ256mr : X86::VMOVAPDYmr;
592 Opc = HasVLX ? X86::VMOVUPDZ256mr : X86::VMOVUPDYmr;
601 Opc = HasVLX ? X86::VMOVNTDQZ256mr : X86::VMOVNTDQYmr;
603 Opc = HasVLX ? X86::VMOVDQA64Z256mr : X86::VMOVDQAYmr;
605 Opc = HasVLX ? X86::VMOVDQU64Z256mr : X86::VMOVDQUYmr;
610 Opc = IsNonTemporal ? X86::VMOVNTPSZmr : X86::VMOVAPSZmr;
612 Opc = X86::VMOVUPSZmr;
617 Opc = IsNonTemporal ? X86::VMOVNTPDZmr : X86::VMOVAPDZmr;
619 Opc = X86::VMOVUPDZmr;
629 Opc = IsNonTemporal ? X86::VMOVNTDQZmr : X86::VMOVDQA64Zmr;
631 Opc = X86::VMOVDQU64Zmr;
635 const MCInstrDesc &Desc = TII.get(Opc);
661 unsigned Opc = 0;
668 case MVT::i8: Opc = X86::MOV8mi; break;
669 case MVT::i16: Opc = X86::MOV16mi; break;
670 case MVT::i32: Opc = X86::MOV32mi; break;
674 Opc = X86::MOV64mi32;
678 if (Opc) {
680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc));
697 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
699 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
702 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
768 unsigned Opc = 0;
779 Opc = X86::MOV64rm;
782 Opc = X86::MOV32rm;
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), LoadReg);
2138 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(*RC) / 8, false,
2140 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC);
2252 const uint16_t *Opc = nullptr;
2255 case MVT::f32: Opc = &OpcTable[0][0]; break;
2256 case MVT::f64: Opc = &OpcTable[1][0]; break;
2260 Register CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpRHSReg, CC);
2261 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg);
2262 Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, RHSReg);
2263 Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, AndReg);
2275 unsigned Opc;
2278 case MVT::i8: Opc = X86::CMOV_GR8; break;
2279 case MVT::i16: Opc = X86::CMOV_GR16; break;
2280 case MVT::i32: Opc = X86::CMOV_GR32; break;
2282 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR16X : X86::CMOV_FR16; break;
2284 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR32X : X86::CMOV_FR32; break;
2286 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR64X : X86::CMOV_FR64; break;
2341 fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC);
2491 unsigned Opc =
2494 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64));
2505 unsigned Opc =
2508 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32));
2619 unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPS2PHZ128rr
2621 InputReg = fastEmitInst_ri(Opc, RC, InputReg, 4);
2624 Opc = Subtarget->hasAVX512() ? X86::VMOVPDI2DIZrr
2627 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
2642 unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPH2PSZ128rr
2644 InputReg = fastEmitInst_r(Opc, RC, InputReg);
2668 unsigned Opc;
2673 case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break;
2674 case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;
2704 TII.get(Opc), DestReg), SrcReg);
2810 unsigned Opc;
2813 case MVT::f32: Opc = SqrtOpc[AVXLevel][0]; break;
2814 case MVT::f64: Opc = SqrtOpc[AVXLevel][1]; break;
2833 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
2897 static const uint16_t Opc[2][4] = {
2908 TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg)
2999 unsigned Opc;
3002 case MVT::i32: Opc = CvtOpc[AVXLevel][IsInputDouble][0]; break;
3003 case MVT::i64: Opc = CvtOpc[AVXLevel][IsInputDouble][1]; break;
3026 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
3045 unsigned Opc;
3053 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r8);
3057 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r16);
3061 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r32);
3065 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r64r64);
3079 Register ResultReg = fastEmitInst_rr(Opc, RC, LHSReg, RHSReg);
3619 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
3623 TII.get(Opc)), FI)
3625 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt;
3627 TII.get(Opc), ResultReg + i), FI);
3752 unsigned Opc = 0;
3758 case MVT::i8: Opc = X86::MOV8ri; break;
3759 case MVT::i16: Opc = X86::MOV16ri; break;
3760 case MVT::i32: Opc = X86::MOV32ri; break;
3763 Opc = X86::MOV32ri64;
3765 Opc = X86::MOV64ri32;
3767 Opc = X86::MOV64ri;
3771 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
3785 unsigned Opc = 0;
3793 Opc = HasAVX512 ? X86::VMOVSSZrm_alt
3799 Opc = HasAVX512 ? X86::VMOVSDZrm_alt
3833 TII.get(Opc), ResultReg);
3843 TII.get(Opc), ResultReg),
3874 unsigned Opc =
3879 TII.get(Opc), ResultReg), AM);
3901 unsigned Opc = 0;
3907 Opc = X86::LD_Fp032;
3911 Opc = X86::LD_Fp064;
3914 Opc = X86::LD_Fp080;
3918 if (Opc) {
3920 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
3944 unsigned Opc =
3951 TII.get(Opc), ResultReg), AM);
3964 unsigned Opc = 0;
3968 Opc = HasAVX512 ? X86::AVX512_FsFLD0SH : X86::FsFLD0SH;
3971 Opc = HasAVX512 ? X86::AVX512_FsFLD0SS
3976 Opc = HasAVX512 ? X86::AVX512_FsFLD0SD
3986 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg);