Lines Matching defs:OpReg

1733         Register OpReg = getRegForValue(TI->getOperand(0));
1734         if (OpReg == 0) return false;
1737           .addReg(OpReg).addImm(1);
1768   Register OpReg = getRegForValue(BI->getCondition());
1769   if (OpReg == 0) return false;
1771   // In case OpReg is a K register, COPY to a GPR
1772   if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
1773     unsigned KOpReg = OpReg;
1774     OpReg = createResultReg(&X86::GR32RegClass);
1776             TII.get(TargetOpcode::COPY), OpReg)
1778     OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, X86::sub_8bit);
1781       .addReg(OpReg)
1790   unsigned CReg = 0, OpReg = 0;
1796     case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1797     case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1798     case Instruction::Shl:  OpReg = X86::SHL8rCL; break;
1806     case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1807     case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1808     case Instruction::Shl:  OpReg = X86::SHL16rCL; break;
1815     case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1816     case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1817     case Instruction::Shl:  OpReg = X86::SHL32rCL; break;
1824     case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1825     case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1826     case Instruction::Shl:  OpReg = X86::SHL64rCL; break;
1852   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(OpReg), ResultReg)
2115     // In case OpReg is a K register, COPY to a GPR
2316     // In case OpReg is a K register, COPY to a GPR
2362       Register OpReg = getRegForValue(Opnd);
2363       if (OpReg == 0)
2369         .addReg(OpReg);
2407   Register OpReg = getRegForValue(I->getOperand(0));
2408   if (OpReg == 0)
2439   Register ResultReg = fastEmitInst_rr(Opcode, RC, ImplicitDefReg, OpReg);
2461   Register OpReg = getRegForValue(I->getOperand(0));
2462   if (OpReg == 0)
2481   MIB.addReg(OpReg);