Lines Matching +full:use +full:- +full:case
1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // the X86 target useful for the compiler back-end and the MC libraries.
14 //===----------------------------------------------------------------------===//
70 // AVX512 embedded rounding control. This should only have values 0-3.
123 /// \returns the type of the first instruction in macro-fusion.
131 case X86::TEST16i16:
132 case X86::TEST16mr:
133 case X86::TEST16ri:
134 case X86::TEST16rr:
135 case X86::TEST32i32:
136 case X86::TEST32mr:
137 case X86::TEST32ri:
138 case X86::TEST32rr:
139 case X86::TEST64i32:
140 case X86::TEST64mr:
141 case X86::TEST64ri32:
142 case X86::TEST64rr:
143 case X86::TEST8i8:
144 case X86::TEST8mr:
145 case X86::TEST8ri:
146 case X86::TEST8rr:
148 case X86::AND16i16:
149 case X86::AND16ri:
150 case X86::AND16ri8:
151 case X86::AND16rm:
152 case X86::AND16rr:
153 case X86::AND32i32:
154 case X86::AND32ri:
155 case X86::AND32ri8:
156 case X86::AND32rm:
157 case X86::AND32rr:
158 case X86::AND64i32:
159 case X86::AND64ri32:
160 case X86::AND64ri8:
161 case X86::AND64rm:
162 case X86::AND64rr:
163 case X86::AND8i8:
164 case X86::AND8ri:
165 case X86::AND8ri8:
166 case X86::AND8rm:
167 case X86::AND8rr:
170 case X86::CMP16i16:
171 case X86::CMP16mr:
172 case X86::CMP16ri:
173 case X86::CMP16ri8:
174 case X86::CMP16rm:
175 case X86::CMP16rr:
176 case X86::CMP32i32:
177 case X86::CMP32mr:
178 case X86::CMP32ri:
179 case X86::CMP32ri8:
180 case X86::CMP32rm:
181 case X86::CMP32rr:
182 case X86::CMP64i32:
183 case X86::CMP64mr:
184 case X86::CMP64ri32:
185 case X86::CMP64ri8:
186 case X86::CMP64rm:
187 case X86::CMP64rr:
188 case X86::CMP8i8:
189 case X86::CMP8mr:
190 case X86::CMP8ri:
191 case X86::CMP8ri8:
192 case X86::CMP8rm:
193 case X86::CMP8rr:
196 case X86::ADD16i16:
197 case X86::ADD16ri:
198 case X86::ADD16ri8:
199 case X86::ADD16rm:
200 case X86::ADD16rr:
201 case X86::ADD32i32:
202 case X86::ADD32ri:
203 case X86::ADD32ri8:
204 case X86::ADD32rm:
205 case X86::ADD32rr:
206 case X86::ADD64i32:
207 case X86::ADD64ri32:
208 case X86::ADD64ri8:
209 case X86::ADD64rm:
210 case X86::ADD64rr:
211 case X86::ADD8i8:
212 case X86::ADD8ri:
213 case X86::ADD8ri8:
214 case X86::ADD8rm:
215 case X86::ADD8rr:
217 case X86::SUB16i16:
218 case X86::SUB16ri:
219 case X86::SUB16ri8:
220 case X86::SUB16rm:
221 case X86::SUB16rr:
222 case X86::SUB32i32:
223 case X86::SUB32ri:
224 case X86::SUB32ri8:
225 case X86::SUB32rm:
226 case X86::SUB32rr:
227 case X86::SUB64i32:
228 case X86::SUB64ri32:
229 case X86::SUB64ri8:
230 case X86::SUB64rm:
231 case X86::SUB64rr:
232 case X86::SUB8i8:
233 case X86::SUB8ri:
234 case X86::SUB8ri8:
235 case X86::SUB8rm:
236 case X86::SUB8rr:
239 case X86::INC16r:
240 case X86::INC16r_alt:
241 case X86::INC32r:
242 case X86::INC32r_alt:
243 case X86::INC64r:
244 case X86::INC8r:
246 case X86::DEC16r:
247 case X86::DEC16r_alt:
248 case X86::DEC32r:
249 case X86::DEC32r_alt:
250 case X86::DEC64r:
251 case X86::DEC8r:
256 /// \returns the type of the second instruction in macro-fusion.
264 case X86::COND_E: // JE,JZ
265 case X86::COND_NE: // JNE,JNZ
266 case X86::COND_L: // JL,JNGE
267 case X86::COND_LE: // JLE,JNG
268 case X86::COND_G: // JG,JNLE
269 case X86::COND_GE: // JGE,JNL
271 case X86::COND_B: // JB,JC
272 case X86::COND_BE: // JNA,JBE
273 case X86::COND_A: // JA,JNBE
274 case X86::COND_AE: // JAE,JNC,JNB
276 case X86::COND_S: // JS
277 case X86::COND_NS: // JNS
278 case X86::COND_P: // JP,JPE
279 case X86::COND_NP: // JNP,JPO
280 case X86::COND_O: // JO
281 case X86::COND_NO: // JNO
293 case X86::FirstMacroFusionInstKind::Test:
294 case X86::FirstMacroFusionInstKind::And:
296 case X86::FirstMacroFusionInstKind::Cmp:
297 case X86::FirstMacroFusionInstKind::AddSub:
300 case X86::FirstMacroFusionInstKind::IncDec:
302 case X86::FirstMacroFusionInstKind::Invalid:
336 case X86::CS:
338 case X86::DS:
340 case X86::ES:
342 case X86::FS:
344 case X86::GS:
346 case X86::SS:
353 /// X86II - This namespace holds all of the target specific flags that
359 //===------------------------------------------------------------------===//
362 /// MO_NO_FLAG - No flag for the operand
364 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
366 /// SYMBOL_LABEL + [. - PICBASELABEL]
368 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
370 /// SYMBOL_LABEL - PICBASELABEL
372 /// MO_GOT - On a symbol operand this indicates that the immediate is the
374 /// See the X86-64 ELF ABI supplement for more details.
377 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
379 /// See the X86-64 ELF ABI supplement for more details.
382 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
385 /// See the X86-64 ELF ABI supplement for more details.
388 /// MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL
392 /// MO_PLT - On a symbol operand this indicates that the immediate is
394 /// See the X86-64 ELF ABI supplement for more details.
397 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
401 /// See 'ELF Handling for Thread-Local Storage' for more details.
404 /// MO_TLSLD - On a symbol operand this indicates that the immediate is
408 /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
409 /// See 'ELF Handling for Thread-Local Storage' for more details.
412 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
417 /// See 'ELF Handling for Thread-Local Storage' for more details.
420 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
421 /// the offset of the GOT entry with the thread-pointer offset for the
422 /// symbol. Used in the x86-64 initial exec TLS access model.
423 /// See 'ELF Handling for Thread-Local Storage' for more details.
426 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
427 /// the absolute address of the GOT entry with the negative thread-pointer
428 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
430 /// See 'ELF Handling for Thread-Local Storage' for more details.
433 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
434 /// the thread-pointer offset for the symbol. Used in the x86-64 local
436 /// See 'ELF Handling for Thread-Local Storage' for more details.
439 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
442 /// See 'ELF Handling for Thread-Local Storage' for more details.
445 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
446 /// the negative thread-pointer offset for the symbol. Used in the IA32
448 /// See 'ELF Handling for Thread-Local Storage' for more details.
451 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
452 /// the offset of the GOT entry with the negative thread-pointer offset for
454 /// See 'ELF Handling for Thread-Local Storage' for more details.
457 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
461 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
463 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
465 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
466 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
467 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
469 /// MO_TLVP - On a symbol operand this indicates that the immediate is
473 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
475 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
477 /// MO_SECREL - On a symbol operand this indicates that the immediate is
481 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
482 /// to be an absolute symbol in range [0,128), so we can use the @ABS8
485 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
492 //===------------------------------------------------------------------===//
496 /// PseudoFrm - This represents an instruction that is a pseudo instruction
500 /// Raw - This form is for instructions that don't have any operands, so
503 /// AddRegFrm - This form is used for instructions like 'push r32' that have
506 /// RawFrmMemOffs - This form is for instructions that store an absolute
509 /// RawFrmSrc - This form is for instructions that use the source index
512 /// RawFrmDst - This form is for instructions that use the destination index
515 /// RawFrmDstSrc - This form is for instructions that use the source index
519 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
520 /// immediates, the first of which is a 16-bit immediate (specified by
521 /// the imm encoding) and the second is a 8-bit fixed value.
523 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
524 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
525 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
528 /// AddCCFrm - This form is used for Jcc that encode the condition code
531 /// PrefixByte - This form is used for instructions that represent a prefix
534 /// MRMDestRegCC - This form is used for the cfcmov instructions, which use
538 /// MRMDestMemCC - This form is used for the cfcmov instructions, which use
542 /// MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM
543 /// byte to specify a destination which in this case is memory and operand 3
548 /// MRMSrcMem - But force to use the SIB field.
550 /// MRMDestMem - But force to use the SIB field.
552 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
553 /// to specify a destination, which in this case is memory.
555 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
556 /// to specify a source, which in this case is memory.
558 /// MRMSrcMem4VOp3 - This form is used for instructions that encode
561 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
562 /// byte to specify the fourth source, which in this case is memory.
564 /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
567 /// MRMXm - This form is used for instructions that use the Mod/RM byte
568 /// to specify a memory source, but doesn't use the middle field. And has
571 /// MRMXm - This form is used for instructions that use the Mod/RM byte
572 /// to specify a memory source, but doesn't use the middle field.
574 /// MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use
584 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
585 /// to specify a destination, which in this case is a register.
587 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
588 /// to specify a source, which in this case is a register.
590 /// MRMSrcReg4VOp3 - This form is used for instructions that encode
593 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
594 /// byte to specify the fourth source, which in this case is a register.
596 /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
599 /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
600 /// to specify a register source, but doesn't use the middle field. And has
603 /// MRMXr - This form is used for instructions that use the Mod/RM byte
604 /// to specify a register source, but doesn't use the middle field.
606 /// MRM0r-MRM7r - Instructions that operate on a register r/m operand and use
616 /// MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but
626 /// MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
692 //===------------------------------------------------------------------===//
694 /// OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
695 /// OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
696 /// 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
697 /// prefix in 16-bit mode.
703 /// AsSize - AdSizeX implies this instruction determines its need of 0x67
713 //===------------------------------------------------------------------===//
714 /// OpPrefix - There are several prefix bytes that are used as opcode
719 /// PD - Prefix code for packed double precision vector floating point
722 /// XS, XD - These prefix codes are for single and double precision scalar
726 //===------------------------------------------------------------------===//
727 /// OpMap - This field determines which opcode map this instruction
728 /// belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
731 /// OB - OneByte - Set if this instruction has a one byte opcode.
733 /// TB - TwoByte - Set if this instruction has a two byte opcode, which
736 /// T8, TA - Prefix after the 0x0F prefix.
739 /// XOP8 - Prefix to include use of imm byte.
741 /// XOP9 - Prefix to exclude use of imm byte.
743 /// XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
745 /// ThreeDNow - This indicates that the instruction uses the
752 /// MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
757 //===------------------------------------------------------------------===//
758 /// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
759 /// They are used to specify GPRs and SSE registers, 64-bit operand size,
764 //===------------------------------------------------------------------===//
765 // This 4-bit field describes the size of an immediate operand. Zero is
778 //===------------------------------------------------------------------===//
779 /// FP Instruction Classification... Zero is non-fp instruction.
780 /// FPTypeMask - Mask for all of the FP types...
783 /// NotFP - The default, set for instructions that do not use FP registers.
785 /// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
787 /// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
789 /// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
792 /// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
796 /// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
799 /// CondMovFP - "2 operand" floating point conditional move instructions.
801 /// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
810 /// 0 means normal, non-SSE instruction.
815 /// LEGACY - encoding using REX/REX2 or w/o opcode prefix.
817 /// VEX - encoding using 0xC4/0xC5
819 /// XOP - Opcode prefix used by XOP instructions.
821 /// EVEX - Specifies that this instruction use EVEX form which provides
822 /// syntax support up to 32 512-bit register operands and up to 7 16-bit
828 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
833 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
834 /// instruction uses 256-bit wide registers. This is usually auto detected
839 /// EVEX_K - Set if this instruction requires masking
842 /// EVEX_Z - Set if this instruction has EVEX.Z field set.
845 /// EVEX_L2 - Set if this instruction has EVEX.L' field set.
848 /// EVEX_B - Set if this instruction has EVEX.B field set.
851 /// The scaling factor for the AVX512's 8-bit compressed displacement.
864 /// For instructions that use VEX encoding only when {vex}, {vex2} or {vex3}
870 /// EVEX_NF - Set if this instruction has EVEX.NF field set.
873 // TwoConditionalOps - Set if this instruction has two conditional operands
902 case X86II::Imm8:
903 case X86II::Imm8PCRel:
904 case X86II::Imm8Reg:
906 case X86II::Imm16:
907 case X86II::Imm16PCRel:
909 case X86II::Imm32:
910 case X86II::Imm32S:
911 case X86II::Imm32PCRel:
913 case X86II::Imm64:
924 case X86II::Imm8PCRel:
925 case X86II::Imm16PCRel:
926 case X86II::Imm32PCRel:
928 case X86II::Imm8:
929 case X86II::Imm8Reg:
930 case X86II::Imm16:
931 case X86II::Imm32:
932 case X86II::Imm32S:
933 case X86II::Imm64:
944 case X86II::Imm32S:
946 case X86II::Imm8:
947 case X86II::Imm8PCRel:
948 case X86II::Imm8Reg:
949 case X86II::Imm16:
950 case X86II::Imm16PCRel:
951 case X86II::Imm32:
952 case X86II::Imm32PCRel:
953 case X86II::Imm64:
963 /// the defs so we have to use some heuristics to find which operands to
971 case 0:
973 case 1:
974 // Common two addr case.
977 // Check for AVX-512 scatter which has a TIED_TO in the second to last
982 case 2:
987 // Check for gather. AVX-512 has the second tied operand early. AVX2
1003 /// \returns operand # for the first field of the memory operand or -1 if no
1015 case X86II::Pseudo:
1016 case X86II::RawFrm:
1017 case X86II::AddRegFrm:
1018 case X86II::RawFrmImm8:
1019 case X86II::RawFrmImm16:
1020 case X86II::RawFrmMemOffs:
1021 case X86II::RawFrmSrc:
1022 case X86II::RawFrmDst:
1023 case X86II::RawFrmDstSrc:
1024 case X86II::AddCCFrm:
1025 case X86II::PrefixByte:
1026 return -1;
1027 case X86II::MRMDestMem:
1028 case X86II::MRMDestMemFSIB:
1029 case X86II::MRMDestMemCC:
1031 case X86II::MRMSrcMem:
1032 case X86II::MRMSrcMemFSIB:
1036 case X86II::MRMSrcMem4VOp3:
1039 case X86II::MRMSrcMemOp4:
1042 case X86II::MRMSrcMemCC:
1044 case X86II::MRMDestMem4VOp3CC:
1048 case X86II::MRMDestReg:
1049 case X86II::MRMDestRegCC:
1050 case X86II::MRMSrcReg:
1051 case X86II::MRMSrcReg4VOp3:
1052 case X86II::MRMSrcRegOp4:
1053 case X86II::MRMSrcRegCC:
1054 case X86II::MRMXrCC:
1055 case X86II::MRMr0:
1056 case X86II::MRMXr:
1057 case X86II::MRM0r:
1058 case X86II::MRM1r:
1059 case X86II::MRM2r:
1060 case X86II::MRM3r:
1061 case X86II::MRM4r:
1062 case X86II::MRM5r:
1063 case X86II::MRM6r:
1064 case X86II::MRM7r:
1065 return -1;
1066 case X86II::MRM0X:
1067 case X86II::MRM1X:
1068 case X86II::MRM2X:
1069 case X86II::MRM3X:
1070 case X86II::MRM4X:
1071 case X86II::MRM5X:
1072 case X86II::MRM6X:
1073 case X86II::MRM7X:
1074 return -1;
1075 case X86II::MRMXmCC:
1076 case X86II::MRMXm:
1077 case X86II::MRM0m:
1078 case X86II::MRM1m:
1079 case X86II::MRM2m:
1080 case X86II::MRM3m:
1081 case X86II::MRM4m:
1082 case X86II::MRM5m:
1083 case X86II::MRM6m:
1084 case X86II::MRM7m:
1087 case X86II::MRM_C0:
1088 case X86II::MRM_C1:
1089 case X86II::MRM_C2:
1090 case X86II::MRM_C3:
1091 case X86II::MRM_C4:
1092 case X86II::MRM_C5:
1093 case X86II::MRM_C6:
1094 case X86II::MRM_C7:
1095 case X86II::MRM_C8:
1096 case X86II::MRM_C9:
1097 case X86II::MRM_CA:
1098 case X86II::MRM_CB:
1099 case X86II::MRM_CC:
1100 case X86II::MRM_CD:
1101 case X86II::MRM_CE:
1102 case X86II::MRM_CF:
1103 case X86II::MRM_D0:
1104 case X86II::MRM_D1:
1105 case X86II::MRM_D2:
1106 case X86II::MRM_D3:
1107 case X86II::MRM_D4:
1108 case X86II::MRM_D5:
1109 case X86II::MRM_D6:
1110 case X86II::MRM_D7:
1111 case X86II::MRM_D8:
1112 case X86II::MRM_D9:
1113 case X86II::MRM_DA:
1114 case X86II::MRM_DB:
1115 case X86II::MRM_DC:
1116 case X86II::MRM_DD:
1117 case X86II::MRM_DE:
1118 case X86II::MRM_DF:
1119 case X86II::MRM_E0:
1120 case X86II::MRM_E1:
1121 case X86II::MRM_E2:
1122 case X86II::MRM_E3:
1123 case X86II::MRM_E4:
1124 case X86II::MRM_E5:
1125 case X86II::MRM_E6:
1126 case X86II::MRM_E7:
1127 case X86II::MRM_E8:
1128 case X86II::MRM_E9:
1129 case X86II::MRM_EA:
1130 case X86II::MRM_EB:
1131 case X86II::MRM_EC:
1132 case X86II::MRM_ED:
1133 case X86II::MRM_EE:
1134 case X86II::MRM_EF:
1135 case X86II::MRM_F0:
1136 case X86II::MRM_F1:
1137 case X86II::MRM_F2:
1138 case X86II::MRM_F3:
1139 case X86II::MRM_F4:
1140 case X86II::MRM_F5:
1141 case X86II::MRM_F6:
1142 case X86II::MRM_F7:
1143 case X86II::MRM_F8:
1144 case X86II::MRM_F9:
1145 case X86II::MRM_FA:
1146 case X86II::MRM_FB:
1147 case X86II::MRM_FC:
1148 case X86II::MRM_FD:
1149 case X86II::MRM_FE:
1150 case X86II::MRM_FF:
1151 return -1;
1157 static_assert(X86::XMM15 - X86::XMM0 == 15,
1158 "XMM0-15 registers are not continuous");
1159 static_assert(X86::XMM31 - X86::XMM16 == 15,
1160 "XMM16-31 registers are not continuous");
1167 static_assert(X86::YMM15 - X86::YMM0 == 15,
1168 "YMM0-15 registers are not continuous");
1169 static_assert(X86::YMM31 - X86::YMM16 == 15,
1170 "YMM16-31 registers are not continuous");
1177 static_assert(X86::ZMM31 - X86::ZMM0 == 31,
1184 static_assert(X86::R31WH - X86::R16 == 95, "EGPRs are not continuous");
1188 /// \returns true if the MachineOperand is a x86-64 extended (r8 or
1204 case X86::R8:
1205 case X86::R9:
1206 case X86::R10:
1207 case X86::R11:
1208 case X86::R12:
1209 case X86::R13:
1210 case X86::R14:
1211 case X86::R15:
1212 case X86::R8D:
1213 case X86::R9D:
1214 case X86::R10D:
1215 case X86::R11D:
1216 case X86::R12D:
1217 case X86::R13D:
1218 case X86::R14D:
1219 case X86::R15D:
1220 case X86::R8W:
1221 case X86::R9W:
1222 case X86::R10W:
1223 case X86::R11W:
1224 case X86::R12W:
1225 case X86::R13W:
1226 case X86::R14W:
1227 case X86::R15W:
1228 case X86::R8B:
1229 case X86::R9B:
1230 case X86::R10B:
1231 case X86::R11B:
1232 case X86::R12B:
1233 case X86::R13B:
1234 case X86::R14B:
1235 case X86::R15B:
1236 case X86::CR8:
1237 case X86::CR9:
1238 case X86::CR10:
1239 case X86::CR11:
1240 case X86::CR12:
1241 case X86::CR13:
1242 case X86::CR14:
1243 case X86::CR15:
1244 case X86::DR8:
1245 case X86::DR9:
1246 case X86::DR10:
1247 case X86::DR11:
1248 case X86::DR12:
1249 case X86::DR13:
1250 case X86::DR14:
1251 case X86::DR15:
1260 // EVEX can always use egpr.
1274 // MAP OB/TB in legacy encoding space can always use egpr except
1279 case X86::XSAVE:
1280 case X86::XSAVE64:
1281 case X86::XSAVEOPT:
1282 case X86::XSAVEOPT64:
1283 case X86::XSAVEC:
1284 case X86::XSAVEC64:
1285 case X86::XSAVES:
1286 case X86::XSAVES64:
1287 case X86::XRSTOR:
1288 case X86::XRSTOR64:
1289 case X86::XRSTORS:
1290 case X86::XRSTORS64:
1331 // If there is no base register and we're in 64-bit mode, we need a SIB
1332 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
1334 case X86::ESP:
1335 case X86::RSP:
1336 case X86::R12:
1337 case X86::R12D:
1338 case X86::R20:
1339 case X86::R20D:
1340 case X86::R28:
1341 case X86::R28D: