Lines Matching defs:SrcRC

114                           const TargetRegisterClass *SrcRC) const;
293       const TargetRegisterClass *SrcRC =
297       if (SrcRC != DstRC) {
305             .addImm(getSubRegIndex(SrcRC));
331     const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg);
333     if (DstRC != SrcRC) {
766 // SrcRC lives on a 128-bit vector class.
768                             const TargetRegisterClass *SrcRC) {
771          (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass);
777     const TargetRegisterClass *SrcRC) const {
779   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
812   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
814   if (!DstRC || !SrcRC)
820   if (canTurnIntoCOPY(DstRC, SrcRC))
821     return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
827   if (DstRC == SrcRC) {
840   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
842   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
941   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
946   if (canTurnIntoCOPY(SrcRC, DstRC))
947     return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
952   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
959   if (SrcRC == DstRC) {
969       .addImm(getSubRegIndex(SrcRC));
1302   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1304   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
1306   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1340   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1343   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||