Lines Matching defs:vvvv
871 insn->vvvv =
872 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid);
1583 // Consume vvvv from an instruction if it has a VEX prefix.
1587 int vvvv;
1589 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
1592 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1594 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1596 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1601 vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
1603 insn->vvvv = static_cast<Reg>(vvvv);
1630 // If non-zero vvvv specified, make sure one of the operands uses it.
1632 needVVVV = hasVVVV && (insn->vvvv != 0);
1643 needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1777 insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
1793 // If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail
2419 translateRegister(mcInst, insn.vvvv);