Lines Matching defs:operand

46 // 6. For each operand, its encoding is an entry from OperandEncoding
50 //    been read.  For example, a register operand could be stored in the R/M
217 // instruction as having them.  Also sets the instruction's default operand,
841 // Consult an operand type to determine the meaning of the reg or R/M field. If
842 // the operand is an XMM operand, for example, an operand would be XMM0 instead
845 // @param insn  - The instruction containing the operand.
846 // @param type  - The operand type.
854 // Consult an operand specifier to determine which of the fixup*Value functions
858 // @param op    - The operand specifier.
1488 // Read an operand from the opcode field of an instruction and interprets it
1489 // appropriately given the operand width. Handles AddRegFrm instructions.
1533 // Consume an immediate operand from an instruction, given the desired operand
1536 // @param insn  - The instruction whose operand is to be read.
1537 // @param size  - The width (in bytes) of the operand.
1773       needVVVV = 0; // Mark that we have found a VVVV operand.
1788       LLVM_DEBUG(dbgs() << "Encountered an operand with an unknown encoding.");
1793   // If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail
1915 ///   register, and appends it as an operand to an MCInst.
1938 /// translateSrcIndex   - Appends a source index operand to an MCInst.
1962 /// translateDstIndex   - Appends a destination index operand to an MCInst.
1983 /// translateImmediate  - Appends an immediate operand to an MCInst.
1987 /// @param operand      - The operand, as stored in the descriptor table.
1990                                const OperandSpecifier &operand,
1995   OperandType type = (OperandType)operand.type;
2002     switch (operand.encoding) {
2041     switch (operand.encoding) {
2072     // operand is 64 bits wide.  Do nothing.
2097     debug("A R/M register operand may not have a SIB byte");
2111     debug("A R/M register operand may not have a base; "
2112           "the operand must be a register.");
2124 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
2126 ///   operand in LLVM's format, and appends it to an MCInst.
2262         debug("A R/M memory operand may not be a register; "
2290 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
2294 /// @param operand      - The operand, as stored in the descriptor table.
2298 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
2300   switch (operand.type) {
2302     debug("Unexpected type for a R/M operand");
2357 /// translateOperand - Translates an operand stored in an internal instruction
2361 /// @param operand      - The operand, as stored in the descriptor table.
2364 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
2367   switch (operand.encoding) {
2369     debug("Unhandled operand encoding during translation");
2379     return translateRM(mcInst, operand, insn, Dis);
2388                        operand,
2422     return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],