Lines Matching defs:IndexReg
437 unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0;
472 unsigned getIndexReg() const { return IndexReg; }
500 // This case mostly happen in inline asm, e.g. Arr[BaseReg + IndexReg]
505 ErrMsg = "BaseReg/IndexReg already set!";
687 // If we already have a BaseReg, then assume this is the IndexReg with
692 if (IndexReg)
694 IndexReg = TmpReg;
746 // If we already have a BaseReg, then assume this is the IndexReg with
751 if (IndexReg)
753 IndexReg = TmpReg;
810 if (IndexReg)
813 IndexReg = Reg;
892 if (IndexReg)
894 IndexReg = TmpReg;
991 // If we already have a BaseReg, then assume this is the IndexReg with
996 if (IndexReg)
998 IndexReg = TmpReg;
1155 unsigned BaseReg, unsigned IndexReg,
1303 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
1308 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1319 if (IndexReg != 0 &&
1320 !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
1321 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1322 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1323 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1324 X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1325 X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1326 X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {
1331 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
1332 IndexReg == X86::EIP || IndexReg == X86::RIP ||
1333 IndexReg == X86::ESP || IndexReg == X86::RSP) {
1348 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1353 if (BaseReg != 0 && IndexReg != 0) {
1355 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1356 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1357 IndexReg == X86::EIZ)) {
1362 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1363 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1364 IndexReg == X86::RIZ)) {
1369 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1370 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1375 (IndexReg != X86::SI && IndexReg != X86::DI)) {
1614 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1623 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1757 unsigned BaseReg, unsigned IndexReg,
1788 if (BaseReg || IndexReg) {
1791 BaseReg && IndexReg));
1798 getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
2655 unsigned IndexReg = SM.getIndexReg();
2656 if (IndexReg && BaseReg == X86::RIP)
2663 (IndexReg == X86::ESP || IndexReg == X86::RSP))
2664 std::swap(BaseReg, IndexReg);
2666 // If BaseReg is a vector register and IndexReg is not, swap them unless
2669 !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
2670 X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
2671 X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
2675 std::swap(BaseReg, IndexReg);
2678 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
2689 (IndexReg == X86::BX || IndexReg == X86::BP))
2690 std::swap(BaseReg, IndexReg);
2692 if ((BaseReg || IndexReg) &&
2693 CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2699 return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale,
2711 ((PtrInOperand && !IndexReg) || SM.getElementSize() > 0)) {
2719 } else if (!BaseReg && !IndexReg && Disp &&
2741 if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister))
2743 getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,
3044 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
3082 } else { // IndexReg Found.
3083 IndexReg = cast<X86MCExpr>(E)->getRegNo();
3088 if (IndexReg == X86::RIP)
3121 if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
3128 if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
3137 if (BaseReg || IndexReg) {
3141 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg);
3161 if (SegReg || BaseReg || IndexReg)
3163 BaseReg, IndexReg, Scale, StartLoc,
3959 /*BaseReg=*/Basereg, /*IndexReg=*/0,