Lines Matching refs:avl
26 (i64 simm7:$stride), (MaskVT true_mask), i32:$avl),
28 (LO7 $stride), $addr, $val, $avl)>;
32 i64:$stride, (MaskVT true_mask), i32:$avl),
34 $stride, $addr, $val, $avl)>;
38 (i64 simm7:$stride), MaskVT:$mask, i32:$avl),
40 (LO7 $stride), $addr, $val, $mask, $avl)>;
44 i64:$stride, MaskVT:$mask, i32:$avl),
46 $stride, $addr, $val, $mask, $avl)>;
60 (MaskVT true_mask), i32:$avl)),
62 (LO7 $stride), $addr, $avl)>;
66 (MaskVT true_mask), i32:$avl)),
68 $stride, PtrVT:$addr, $avl)>;
72 MaskVT:$mask, i32:$avl)),
75 (VMULULivml (LO7 $stride), (VSEQl $avl), $mask, $avl),
76 $mask, $avl),
79 $avl)>;
82 PtrVT:$addr, i64:$stride, MaskVT:$mask, i32:$avl)),
85 (VMULULrvml $stride, (VSEQl $avl), $mask, $avl),
86 $mask, $avl),
89 $avl)>;
103 PtrVT:$addr, (MaskVT true_mask), i32:$avl)),
104 (!cast<Instruction>(GTPrefix#"vizl") $addr, 0, 0, $avl)>;
106 def : Pat<(DataVT (vvp_gather PtrVT:$addr, MaskVT:$mask, i32:$avl)),
107 (!cast<Instruction>(GTPrefix#"vizml") $addr, 0, 0, $mask, $avl)>;
120 DataVT:$data, PtrVT:$addr, (MaskVT true_mask), i32:$avl),
121 (!cast<Instruction>(SCPrefix#"vizvl") $addr, 0, 0, $data, $avl)>;
124 DataVT:$data, PtrVT:$addr, MaskVT:$mask, i32:$avl),
125 (!cast<Instruction>(SCPrefix#"vizvml") $addr, 0, 0, $data, $mask, $avl)>;
147 i32:$avl),
148 (VXORmvml_v (i32 1), $vx, $mask, $avl, $vfalse)>;
151 def : Pat<(vvp_fneg DataVT:$vx, (v256i1 true_mask), i32:$avl),
152 (VXORmvl (i32 1), $vx, $avl)>;
155 def : Pat<(vvp_fneg DataVT:$vx, v256i1:$mask, i32:$avl),
156 (VXORmvml (i32 1), $vx, $mask, $avl)>;
168 i32:$avl),
169 (v512f32 (PVXORrvml_v (packed_fneg_imm ), $vx, $mask, $avl, $vfalse))>;
172 def : Pat<(vvp_fneg v512f32:$vx, (v512i1 true_mask), i32:$avl),
173 (v512f32 (PVXORrvl (packed_fneg_imm ), $vx, $avl))>;
176 def : Pat<(vvp_fneg v512f32:$vx, v512i1:$mask, i32:$avl),
177 (v512f32 (PVXORrvml (packed_fneg_imm ), $vx, $mask, $avl))>;
205 i32:$avl),
207 ScalarVT:$sx, $vy, $avl)>;
212 i32:$avl),
214 ScalarVT:$sx, $vy, $mask, $avl)>;
241 i32:$avl),
243 $vx, ScalarVT:$sy, $avl)>;
248 i32:$avl),
250 $vx, ScalarVT:$sy, $mask, $avl)>;
280 i32:$avl),
282 $vx, $vy, $avl)>;
288 i32:$avl),
290 $vx, $vy, $mask, $avl)>;
435 i32:$avl),
437 $vx, $vy, $vz, $mask, $avl, $vfalse)>;
441 (MaskVT true_mask), i32:$avl),
443 $vx, $vy, $vz, $avl)>;
447 MaskVT:$mask, i32:$avl),
449 $vx, $vy, $vz, $mask, $avl)>;
463 i32:$avl),
465 $sx, $vy, $vz, $mask, $avl, $vfalse)>;
470 (MaskVT true_mask), i32:$avl),
472 $sx, $vy, $vz, $avl)>;
477 MaskVT:$mask, i32:$avl),
479 $sx, $vy, $vz, $mask, $avl)>;
493 i32:$avl),
496 $mask, $avl, $vfalse)>;
501 (MaskVT true_mask), i32:$avl),
503 $vx, $sy, $vz, $avl)>;
508 MaskVT:$mask, i32:$avl),
510 $vx, $sy, $vz, $mask, $avl)>;
546 i32:$avl),
548 $vfalse, $vtrue, $vm, $avl, $vfalse)>;