Lines Matching full:ve
1 //===-- VEInstrInfo.cpp - VE Instruction Information ----------------------===//
9 // This file contains the VE implementation of the TargetInstrInfo class.
14 #include "VE.h"
28 #define DEBUG_TYPE "ve-instr-info"
39 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {}
98 using namespace llvm::VE;
101 // VE has other branch relative always instructions for word/double/float,
113 using namespace llvm::VE;
125 using namespace llvm::VE;
129 // VE has other branch always instructions for word/double/float, but
233 "VE branch conditions should have three component!");
238 BuildMI(&MBB, DL, get(VE::BRCFLa_t))
254 opc[0] = VE::BRCFWir;
255 opc[1] = VE::BRCFWrr;
257 opc[0] = VE::BRCFLir;
258 opc[1] = VE::BRCFLrr;
262 opc[0] = VE::BRCFSir;
263 opc[1] = VE::BRCFSrr;
265 opc[0] = VE::BRCFDir;
266 opc[1] = VE::BRCFDrr;
286 BuildMI(&MBB, DL, get(VE::BRCFLa_t))
322 return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||
323 VE::F32RegClass.contains(Reg);
339 if (MCID.getOpcode() == VE::ORri) {
344 } else if (MCID.getOpcode() == VE::ANDMmm) {
347 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc);
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg)
368 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) {
376 Register TmpReg = VE::SX16;
377 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32);
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg)
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg)
387 } else if (VE::VMRegClass.contains(DestReg, SrcReg)) {
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg)
389 .addReg(VE::VM0)
391 } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) {
393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd};
395 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm),
397 } else if (VE::F128RegClass.contains(DestReg, SrcReg)) {
399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};
401 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri),
418 if (MI.getOpcode() == VE::LDrii || // I64
419 MI.getOpcode() == VE::LDLSXrii || // I32
420 MI.getOpcode() == VE::LDUrii || // F32
421 MI.getOpcode() == VE::LDQrii || // F128 (pseudo)
422 MI.getOpcode() == VE::LDVMrii || // VM (pseudo)
423 MI.getOpcode() == VE::LDVM512rii // VM512 (pseudo)
442 if (MI.getOpcode() == VE::STrii || // I64
443 MI.getOpcode() == VE::STLrii || // I32
444 MI.getOpcode() == VE::STUrii || // F32
445 MI.getOpcode() == VE::STQrii || // F128 (pseudo)
446 MI.getOpcode() == VE::STVMrii || // VM (pseudo)
447 MI.getOpcode() == VE::STVM512rii // VM512 (pseudo)
476 if (RC == &VE::I64RegClass) {
477 BuildMI(MBB, I, DL, get(VE::STrii))
483 } else if (RC == &VE::I32RegClass) {
484 BuildMI(MBB, I, DL, get(VE::STLrii))
490 } else if (RC == &VE::F32RegClass) {
491 BuildMI(MBB, I, DL, get(VE::STUrii))
497 } else if (VE::F128RegClass.hasSubClassEq(RC)) {
498 BuildMI(MBB, I, DL, get(VE::STQrii))
504 } else if (RC == &VE::VMRegClass) {
505 BuildMI(MBB, I, DL, get(VE::STVMrii))
511 } else if (VE::VM512RegClass.hasSubClassEq(RC)) {
512 BuildMI(MBB, I, DL, get(VE::STVM512rii))
538 if (RC == &VE::I64RegClass) {
539 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg)
544 } else if (RC == &VE::I32RegClass) {
545 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg)
550 } else if (RC == &VE::F32RegClass) {
551 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg)
556 } else if (VE::F128RegClass.hasSubClassEq(RC)) {
557 BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg)
562 } else if (RC == &VE::VMRegClass) {
563 BuildMI(MBB, I, DL, get(VE::LDVMrii), DestReg)
568 } else if (VE::VM512RegClass.hasSubClassEq(RC)) {
569 BuildMI(MBB, I, DL, get(VE::LDVM512rii), DestReg)
587 case VE::ORim:
588 // General move small immediate instruction on VE.
598 case VE::LEAzii:
599 // General move immediate instruction on VE.
647 using namespace llvm::VE;
763 GlobalBaseReg = VE::SX15;
770 BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg);
776 return (reg - VE::VMP0) * 2 + VE::VM0;
799 case VE::NEGMy:
847 {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}},
848 {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}},
849 {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}},
850 {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}},
851 {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}},
852 {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}},
878 case VE::EXTEND_STACK: {
881 case VE::EXTEND_STACK_GUARD: {
885 case VE::GETSTACKTOP: {
889 case VE::ANDMyy:
890 expandPseudoLogM(MI, get(VE::ANDMmm));
892 case VE::ORMyy:
893 expandPseudoLogM(MI, get(VE::ORMmm));
895 case VE::XORMyy:
896 expandPseudoLogM(MI, get(VE::XORMmm));
898 case VE::EQVMyy:
899 expandPseudoLogM(MI, get(VE::EQVMmm));
901 case VE::NNDMyy:
902 expandPseudoLogM(MI, get(VE::NNDMmm));
904 case VE::NEGMy:
905 expandPseudoLogM(MI, get(VE::NEGMm));
908 case VE::LVMyir:
909 case VE::LVMyim:
910 case VE::LVMyir_y:
911 case VE::LVMyim_y: {
916 MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y;
917 Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister;
928 case VE::LVMyir:
929 BuildMI(*MBB, MI, DL, get(VE::LVMir))
934 case VE::LVMyim:
935 BuildMI(*MBB, MI, DL, get(VE::LVMim))
940 case VE::LVMyir_y:
943 BuildMI(*MBB, MI, DL, get(VE::LVMir_m))
949 case VE::LVMyim_y:
952 BuildMI(*MBB, MI, DL, get(VE::LVMim_m))
962 case VE::SVMyi: {
976 BuildMI(*MBB, MI, DL, get(VE::SVMmi), Dest).addReg(VMZ).addImm(Imm);
985 case VE::VFMKyal:
986 case VE::VFMKynal:
987 case VE::VFMKWyvl:
988 case VE::VFMKWyvyl:
989 case VE::VFMKSyvl:
990 case VE::VFMKSyvyl:
1037 BuildMI(BB, dl, TII.get(VE::BRCFLrr_t))
1039 .addReg(VE::SX11) // %sp
1040 .addReg(VE::SX8) // %sl
1048 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61)
1049 .addReg(VE::SX14)
1052 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62)
1053 .addReg(VE::SX0)
1055 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63)
1059 BuildMI(BB, dl, TII.get(VE::SHMLri))
1060 .addReg(VE::SX61)
1062 .addReg(VE::SX63);
1063 BuildMI(BB, dl, TII.get(VE::SHMLri))
1064 .addReg(VE::SX61)
1066 .addReg(VE::SX8);
1067 BuildMI(BB, dl, TII.get(VE::SHMLri))
1068 .addReg(VE::SX61)
1070 .addReg(VE::SX11);
1071 BuildMI(BB, dl, TII.get(VE::MONC));
1073 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0)
1074 .addReg(VE::SX62)
1095 // The VE ABI requires a reserved area at the top of stack as described
1103 BuildMI(*MBB, MI, DL, TII.get(VE::LEArii))
1105 .addReg(VE::SX11)