Lines Matching defs:Opcode

40   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
41   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
42   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
43   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
44   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
45   bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
109 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
110 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
112     MI.setDesc(TII->get(Opcode));
118 // Change MI's opcode to Opcode if register operands 0 and 1 have a
120 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
123     MI.setDesc(TII->get(Opcode));
129 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
132 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
136     MI.setDesc(TII->get(Opcode));
145 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
146   if (LiveRegs.available(SystemZ::CC) && shortenOn001(MI, Opcode)) {
156 // have a 4-bit encoding then change it to Opcode, which has operand order:
158 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
169     MI.setDesc(TII->get(Opcode));
180 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) {
196     MI.setDesc(TII->get(Opcode));