Lines Matching +full:16 +full:- +full:bits
1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
27 // Some instructions come in pairs, one having a 12-bit displacement
28 // and the other having a 20-bit displacement. Both instructions in
34 // Many register-based <INSN>R instructions have a memory-based <INSN>
40 // MemKey identifies a targe reg-mem opcode, while MemType can be either
46 // Many distinct-operands instructions have older 2-operand equivalents.
47 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
60 // True if this instruction has a 20-bit displacement field.
66 // True if this is a 128-bit pseudo instruction that combines two 64-bit
71 bits<5> AccessBytes = 0;
76 bits<4> CCValues = 0;
81 bits<4> CompareZeroCCMask = 0;
92 // instruction sets this flag along with a non-zero CCValues field, it is
106 let TSFlags{9-5} = AccessBytes;
107 let TSFlags{13-10} = CCValues;
108 let TSFlags{17-14} = CompareZeroCCMask;
115 //===----------------------------------------------------------------------===//
117 //===----------------------------------------------------------------------===//
119 // Return the version of an instruction that has an unsigned 12-bit
129 // Return the version of an instruction that has a signed 20-bit displacement.
157 // Return the 2-operand form of a 3-operand instruction.
166 //===----------------------------------------------------------------------===//
168 //===----------------------------------------------------------------------===//
172 // bits<4> Rn : register input or output for operand n
173 // bits<5> Vn : vector register input or output for operand n
174 // bits<m> In : immediate value of width m for operand n
175 // bits<4> Bn : base register for address operand n
176 // bits<m> Dn : displacement for address operand n
177 // bits<5> Vn : vector index for address operand n
178 // bits<4> Xn : index register for address operand n
179 // bits<4> Mn : mode value for operand n
185 //===----------------------------------------------------------------------===//
187 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
189 field bits<16> Inst;
190 field bits<16> SoftFail = 0;
195 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
197 field bits<16> Inst;
198 field bits<16> SoftFail = 0;
200 bits<8> I1;
202 let Inst{15-8} = op;
203 let Inst{7-0} = I1;
206 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
208 field bits<32> Inst;
209 field bits<32> SoftFail = 0;
211 bits<4> I1;
212 bits<4> I2;
214 let Inst{31-16} = op;
215 let Inst{15-8} = 0;
216 let Inst{7-4} = I1;
217 let Inst{3-0} = I2;
220 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
222 field bits<48> Inst;
223 field bits<48> SoftFail = 0;
225 bits<4> M1;
226 bits<12> RI2;
227 bits<24> RI3;
229 let Inst{47-40} = op;
230 let Inst{39-36} = M1;
231 let Inst{35-24} = RI2;
232 let Inst{23-0} = RI3;
235 class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
237 field bits<32> Inst;
238 field bits<32> SoftFail = 0;
240 bits<4> R1;
241 bits<16> I2;
243 let Inst{31-24} = op{11-4};
244 let Inst{23-20} = R1;
245 let Inst{19-16} = op{3-0};
246 let Inst{15-0} = I2;
249 class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
251 field bits<32> Inst;
252 field bits<32> SoftFail = 0;
254 bits<4> R1;
255 bits<16> RI2;
257 let Inst{31-24} = op{11-4};
258 let Inst{23-20} = R1;
259 let Inst{19-16} = op{3-0};
260 let Inst{15-0} = RI2;
263 class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
265 field bits<32> Inst;
266 field bits<32> SoftFail = 0;
268 bits<4> M1;
269 bits<16> RI2;
271 let Inst{31-24} = op{11-4};
272 let Inst{23-20} = M1;
273 let Inst{19-16} = op{3-0};
274 let Inst{15-0} = RI2;
277 class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
279 field bits<48> Inst;
280 field bits<48> SoftFail = 0;
282 bits<4> R1;
283 bits<16> I2;
284 bits<4> M3;
286 let Inst{47-40} = op{15-8};
287 let Inst{39-36} = R1;
288 let Inst{35-32} = 0;
289 let Inst{31-16} = I2;
290 let Inst{15-12} = M3;
291 let Inst{11-8} = 0;
292 let Inst{7-0} = op{7-0};
295 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
297 field bits<48> Inst;
298 field bits<48> SoftFail = 0;
300 bits<4> R1;
301 bits<4> R2;
302 bits<4> M3;
303 bits<16> RI4;
305 let Inst{47-40} = op{15-8};
306 let Inst{39-36} = R1;
307 let Inst{35-32} = R2;
308 let Inst{31-16} = RI4;
309 let Inst{15-12} = M3;
310 let Inst{11-8} = 0;
311 let Inst{7-0} = op{7-0};
314 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
316 field bits<48> Inst;
317 field bits<48> SoftFail = 0;
319 bits<4> R1;
320 bits<8> I2;
321 bits<4> M3;
322 bits<16> RI4;
324 let Inst{47-40} = op{15-8};
325 let Inst{39-36} = R1;
326 let Inst{35-32} = M3;
327 let Inst{31-16} = RI4;
328 let Inst{15-8} = I2;
329 let Inst{7-0} = op{7-0};
332 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
334 field bits<48> Inst;
335 field bits<48> SoftFail = 0;
337 bits<4> R1;
338 bits<4> R3;
339 bits<16> I2;
341 let Inst{47-40} = op{15-8};
342 let Inst{39-36} = R1;
343 let Inst{35-32} = R3;
344 let Inst{31-16} = I2;
345 let Inst{15-8} = 0;
346 let Inst{7-0} = op{7-0};
349 class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
351 field bits<48> Inst;
352 field bits<48> SoftFail = 0;
354 bits<4> R1;
355 bits<4> R3;
356 bits<16> RI2;
358 let Inst{47-40} = op{15-8};
359 let Inst{39-36} = R1;
360 let Inst{35-32} = R3;
361 let Inst{31-16} = RI2;
362 let Inst{15-8} = 0;
363 let Inst{7-0} = op{7-0};
366 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
367 bits<8> I3Or = 0, bits<8> I4Or = 0>
369 field bits<48> Inst;
370 field bits<48> SoftFail = 0;
372 bits<4> R1;
373 bits<4> R2;
374 bits<8> I3;
375 bits<8> I4;
376 bits<8> I5;
378 let Inst{47-40} = op{15-8};
379 let Inst{39-36} = R1;
380 let Inst{35-32} = R2;
396 let Inst{16} = !if(I4Or{0}, 1, I4{0});
397 let Inst{15-8} = I5;
398 let Inst{7-0} = op{7-0};
401 class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
403 field bits<48> Inst;
404 field bits<48> SoftFail = 0;
406 bits<4> R1;
407 bits<4> M3;
408 bits<16> I2;
410 let Inst{47-40} = op{15-8};
411 let Inst{39-36} = R1;
412 let Inst{35-32} = M3;
413 let Inst{31-16} = I2;
414 let Inst{15-8} = 0;
415 let Inst{7-0} = op{7-0};
418 class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
420 field bits<48> Inst;
421 field bits<48> SoftFail = 0;
423 bits<4> R1;
424 bits<32> I2;
426 let Inst{47-40} = op{11-4};
427 let Inst{39-36} = R1;
428 let Inst{35-32} = op{3-0};
429 let Inst{31-0} = I2;
432 class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
434 field bits<48> Inst;
435 field bits<48> SoftFail = 0;
437 bits<4> R1;
438 bits<32> RI2;
440 let Inst{47-40} = op{11-4};
441 let Inst{39-36} = R1;
442 let Inst{35-32} = op{3-0};
443 let Inst{31-0} = RI2;
446 class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
448 field bits<48> Inst;
449 field bits<48> SoftFail = 0;
451 bits<4> M1;
452 bits<32> RI2;
454 let Inst{47-40} = op{11-4};
455 let Inst{39-36} = M1;
456 let Inst{35-32} = op{3-0};
457 let Inst{31-0} = RI2;
460 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
462 field bits<48> Inst;
463 field bits<48> SoftFail = 0;
465 bits<4> R1;
466 bits<8> I2;
467 bits<4> M3;
468 bits<4> B4;
469 bits<12> D4;
471 let Inst{47-40} = op{15-8};
472 let Inst{39-36} = R1;
473 let Inst{35-32} = M3;
474 let Inst{31-28} = B4;
475 let Inst{27-16} = D4;
476 let Inst{15-8} = I2;
477 let Inst{7-0} = op{7-0};
480 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
482 field bits<16> Inst;
483 field bits<16> SoftFail = 0;
485 bits<4> R1;
486 bits<4> R2;
488 let Inst{15-8} = op;
489 let Inst{7-4} = R1;
490 let Inst{3-0} = R2;
493 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
495 field bits<32> Inst;
496 field bits<32> SoftFail = 0;
498 bits<4> R1;
499 bits<4> R3;
500 bits<4> R2;
502 let Inst{31-16} = op;
503 let Inst{15-12} = R1;
504 let Inst{11-8} = 0;
505 let Inst{7-4} = R3;
506 let Inst{3-0} = R2;
509 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
511 field bits<32> Inst;
512 field bits<32> SoftFail = 0;
514 bits<4> R1;
515 bits<4> R2;
517 let Inst{31-16} = op;
518 let Inst{15-8} = 0;
519 let Inst{7-4} = R1;
520 let Inst{3-0} = R2;
523 class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
525 field bits<32> Inst;
526 field bits<32> SoftFail = 0;
528 bits<4> R1;
529 bits<4> R2;
530 bits<4> R3;
531 bits<4> M4;
533 let Inst{31-16} = op;
534 let Inst{15-12} = R3;
535 let Inst{11-8} = M4;
536 let Inst{7-4} = R1;
537 let Inst{3-0} = R2;
540 class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
542 field bits<32> Inst;
543 field bits<32> SoftFail = 0;
545 bits<4> R1;
546 bits<4> R2;
547 bits<4> R3;
548 bits<4> M4;
550 let Inst{31-16} = op;
551 let Inst{15-12} = R3;
552 let Inst{11-8} = M4;
553 let Inst{7-4} = R1;
554 let Inst{3-0} = R2;
557 class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
559 field bits<32> Inst;
560 field bits<32> SoftFail = 0;
562 bits<4> R1;
563 bits<4> R2;
564 bits<4> M3;
566 let Inst{31-16} = op;
567 let Inst{15-12} = M3;
568 let Inst{11-8} = 0;
569 let Inst{7-4} = R1;
570 let Inst{3-0} = R2;
573 class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
575 field bits<32> Inst;
576 field bits<32> SoftFail = 0;
578 bits<4> R1;
579 bits<4> R2;
580 bits<4> M4;
582 let Inst{31-16} = op;
583 let Inst{15-12} = 0;
584 let Inst{11-8} = M4;
585 let Inst{7-4} = R1;
586 let Inst{3-0} = R2;
589 class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
591 field bits<32> Inst;
592 field bits<32> SoftFail = 0;
594 bits<4> R1;
595 bits<4> R2;
596 bits<4> M3;
597 bits<4> M4;
599 let Inst{31-16} = op;
600 let Inst{15-12} = M3;
601 let Inst{11-8} = M4;
602 let Inst{7-4} = R1;
603 let Inst{3-0} = R2;
606 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
608 field bits<48> Inst;
609 field bits<48> SoftFail = 0;
611 bits<4> R1;
612 bits<4> R2;
613 bits<4> M3;
614 bits<4> B4;
615 bits<12> D4;
617 let Inst{47-40} = op{15-8};
618 let Inst{39-36} = R1;
619 let Inst{35-32} = R2;
620 let Inst{31-28} = B4;
621 let Inst{27-16} = D4;
622 let Inst{15-12} = M3;
623 let Inst{11-8} = 0;
624 let Inst{7-0} = op{7-0};
627 class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
629 field bits<32> Inst;
630 field bits<32> SoftFail = 0;
632 bits<4> R1;
633 bits<4> X2;
634 bits<4> B2;
635 bits<12> D2;
637 let Inst{31-24} = op;
638 let Inst{23-20} = R1;
639 let Inst{19-16} = X2;
640 let Inst{15-12} = B2;
641 let Inst{11-0} = D2;
646 class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
648 field bits<32> Inst;
649 field bits<32> SoftFail = 0;
651 bits<4> M1;
652 bits<4> X2;
653 bits<4> B2;
654 bits<12> D2;
656 let Inst{31-24} = op;
657 let Inst{23-20} = M1;
658 let Inst{19-16} = X2;
659 let Inst{15-12} = B2;
660 let Inst{11-0} = D2;
665 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
667 field bits<48> Inst;
668 field bits<48> SoftFail = 0;
670 bits<4> R1;
671 bits<4> X2;
672 bits<4> B2;
673 bits<12> D2;
674 bits<4> M3;
676 let Inst{47-40} = op{15-8};
677 let Inst{39-36} = R1;
678 let Inst{35-32} = X2;
679 let Inst{31-28} = B2;
680 let Inst{27-16} = D2;
681 let Inst{15-12} = M3;
682 let Inst{11-8} = 0;
683 let Inst{7-0} = op{7-0};
688 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
690 field bits<48> Inst;
691 field bits<48> SoftFail = 0;
693 bits<4> R1;
694 bits<4> R3;
695 bits<4> X2;
696 bits<4> B2;
697 bits<12> D2;
699 let Inst{47-40} = op{15-8};
700 let Inst{39-36} = R3;
701 let Inst{35-32} = X2;
702 let Inst{31-28} = B2;
703 let Inst{27-16} = D2;
704 let Inst{15-12} = R1;
705 let Inst{11-8} = 0;
706 let Inst{7-0} = op{7-0};
711 class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
713 field bits<48> Inst;
714 field bits<48> SoftFail = 0;
716 bits<4> R1;
717 bits<4> X2;
718 bits<4> B2;
719 bits<20> D2;
721 let Inst{47-40} = op{15-8};
722 let Inst{39-36} = R1;
723 let Inst{35-32} = X2;
724 let Inst{31-28} = B2;
725 let Inst{27-16} = D2{11-0};
726 let Inst{15-8} = D2{19-12};
727 let Inst{7-0} = op{7-0};
733 class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
735 field bits<48> Inst;
736 field bits<48> SoftFail = 0;
738 bits<4> M1;
739 bits<4> X2;
740 bits<4> B2;
741 bits<20> D2;
743 let Inst{47-40} = op{15-8};
744 let Inst{39-36} = M1;
745 let Inst{35-32} = X2;
746 let Inst{31-28} = B2;
747 let Inst{27-16} = D2{11-0};
748 let Inst{15-8} = D2{19-12};
749 let Inst{7-0} = op{7-0};
755 class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
757 field bits<32> Inst;
758 field bits<32> SoftFail = 0;
760 bits<4> R1;
761 bits<4> R3;
762 bits<4> B2;
763 bits<12> D2;
765 let Inst{31-24} = op;
766 let Inst{23-20} = R1;
767 let Inst{19-16} = R3;
768 let Inst{15-12} = B2;
769 let Inst{11-0} = D2;
772 class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
774 field bits<32> Inst;
775 field bits<32> SoftFail = 0;
777 bits<4> R1;
778 bits<4> M3;
779 bits<4> B2;
780 bits<12> D2;
782 let Inst{31-24} = op;
783 let Inst{23-20} = R1;
784 let Inst{19-16} = M3;
785 let Inst{15-12} = B2;
786 let Inst{11-0} = D2;
789 class InstRSEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
791 field bits<48> Inst;
792 field bits<48> SoftFail = 0;
794 bits<4> R1;
795 bits<4> R3;
796 bits<4> B2;
797 bits<12> D2;
799 let Inst{47-40} = op{15-8};
800 let Inst{39-36} = R1;
801 let Inst{35-32} = R3;
802 let Inst{31-28} = B2;
803 let Inst{27-16} = D2;
804 let Inst{15-8} = 0;
805 let Inst{7-0} = op{7-0};
808 class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
810 field bits<32> Inst;
811 field bits<32> SoftFail = 0;
813 bits<4> R1;
814 bits<4> R3;
815 bits<16> RI2;
817 let Inst{31-24} = op;
818 let Inst{23-20} = R1;
819 let Inst{19-16} = R3;
820 let Inst{15-0} = RI2;
823 class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
825 field bits<48> Inst;
826 field bits<48> SoftFail = 0;
828 bits<4> B1;
829 bits<12> D1;
830 bits<4> L1;
832 let Inst{47-40} = op{15-8};
833 let Inst{39-36} = L1;
834 let Inst{35-32} = 0;
835 let Inst{31-28} = B1;
836 let Inst{27-16} = D1;
837 let Inst{15-8} = 0;
838 let Inst{7-0} = op{7-0};
841 class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
843 field bits<48> Inst;
844 field bits<48> SoftFail = 0;
846 bits<4> R1;
847 bits<4> B2;
848 bits<12> D2;
849 bits<8> L2;
850 bits<4> M3;
852 let Inst{47-40} = op{15-8};
853 let Inst{39-32} = L2;
854 let Inst{31-28} = B2;
855 let Inst{27-16} = D2;
856 let Inst{15-12} = R1;
857 let Inst{11-8} = M3;
858 let Inst{7-0} = op{7-0};
861 class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
863 field bits<48> Inst;
864 field bits<48> SoftFail = 0;
866 bits<4> R1;
867 bits<4> R3;
868 bits<4> B2;
869 bits<20> D2;
871 let Inst{47-40} = op{15-8};
872 let Inst{39-36} = R1;
873 let Inst{35-32} = R3;
874 let Inst{31-28} = B2;
875 let Inst{27-16} = D2{11-0};
876 let Inst{15-8} = D2{19-12};
877 let Inst{7-0} = op{7-0};
882 class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
884 field bits<48> Inst;
885 field bits<48> SoftFail = 0;
887 bits<4> R1;
888 bits<4> M3;
889 bits<4> B2;
890 bits<20> D2;
892 let Inst{47-40} = op{15-8};
893 let Inst{39-36} = R1;
894 let Inst{35-32} = M3;
895 let Inst{31-28} = B2;
896 let Inst{27-16} = D2{11-0};
897 let Inst{15-8} = D2{19-12};
898 let Inst{7-0} = op{7-0};
903 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
905 field bits<32> Inst;
906 field bits<32> SoftFail = 0;
908 bits<4> B1;
909 bits<12> D1;
910 bits<8> I2;
912 let Inst{31-24} = op;
913 let Inst{23-16} = I2;
914 let Inst{15-12} = B1;
915 let Inst{11-0} = D1;
918 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
920 field bits<48> Inst;
921 field bits<48> SoftFail = 0;
923 bits<4> B1;
924 bits<12> D1;
925 bits<16> I2;
927 let Inst{47-32} = op;
928 let Inst{31-28} = B1;
929 let Inst{27-16} = D1;
930 let Inst{15-0} = I2;
933 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
935 field bits<48> Inst;
936 field bits<48> SoftFail = 0;
938 bits<4> B1;
939 bits<20> D1;
940 bits<8> I2;
942 let Inst{47-40} = op{15-8};
943 let Inst{39-32} = I2;
944 let Inst{31-28} = B1;
945 let Inst{27-16} = D1{11-0};
946 let Inst{15-8} = D1{19-12};
947 let Inst{7-0} = op{7-0};
952 class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
954 field bits<48> Inst;
955 field bits<48> SoftFail = 0;
957 bits<4> M1;
958 bits<16> RI2;
959 bits<4> B3;
960 bits<12> D3;
962 let Inst{47-40} = op;
963 let Inst{39-36} = M1;
964 let Inst{35-32} = 0;
965 let Inst{31-28} = B3;
966 let Inst{27-16} = D3;
967 let Inst{15-0} = RI2;
970 class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
972 field bits<48> Inst;
973 field bits<48> SoftFail = 0;
975 bits<4> B1;
976 bits<12> D1;
977 bits<8> L1;
978 bits<4> B2;
979 bits<12> D2;
981 let Inst{47-40} = op;
982 let Inst{39-32} = L1;
983 let Inst{31-28} = B1;
984 let Inst{27-16} = D1;
985 let Inst{15-12} = B2;
986 let Inst{11-0} = D2;
989 class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
991 field bits<48> Inst;
992 field bits<48> SoftFail = 0;
994 bits<4> B1;
995 bits<12> D1;
996 bits<4> L1;
997 bits<4> B2;
998 bits<12> D2;
999 bits<4> L2;
1001 let Inst{47-40} = op;
1002 let Inst{39-36} = L1;
1003 let Inst{35-32} = L2;
1004 let Inst{31-28} = B1;
1005 let Inst{27-16} = D1;
1006 let Inst{15-12} = B2;
1007 let Inst{11-0} = D2;
1010 class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1012 field bits<48> Inst;
1013 field bits<48> SoftFail = 0;
1015 bits<4> B1;
1016 bits<12> D1;
1017 bits<4> L1;
1018 bits<4> B2;
1019 bits<12> D2;
1020 bits<4> I3;
1022 let Inst{47-40} = op;
1023 let Inst{39-36} = L1;
1024 let Inst{35-32} = I3;
1025 let Inst{31-28} = B1;
1026 let Inst{27-16} = D1;
1027 let Inst{15-12} = B2;
1028 let Inst{11-0} = D2;
1031 class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1033 field bits<48> Inst;
1034 field bits<48> SoftFail = 0;
1036 bits<4> R1;
1037 bits<4> B1;
1038 bits<12> D1;
1039 bits<4> B2;
1040 bits<12> D2;
1041 bits<4> R3;
1043 let Inst{47-40} = op;
1044 let Inst{39-36} = R1;
1045 let Inst{35-32} = R3;
1046 let Inst{31-28} = B1;
1047 let Inst{27-16} = D1;
1048 let Inst{15-12} = B2;
1049 let Inst{11-0} = D2;
1052 class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1054 field bits<48> Inst;
1055 field bits<48> SoftFail = 0;
1057 bits<4> R1;
1058 bits<4> B2;
1059 bits<12> D2;
1060 bits<4> R3;
1061 bits<4> B4;
1062 bits<12> D4;
1064 let Inst{47-40} = op;
1065 let Inst{39-36} = R1;
1066 let Inst{35-32} = R3;
1067 let Inst{31-28} = B2;
1068 let Inst{27-16} = D2;
1069 let Inst{15-12} = B4;
1070 let Inst{11-0} = D4;
1073 class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1075 field bits<48> Inst;
1076 field bits<48> SoftFail = 0;
1078 bits<4> B1;
1079 bits<12> D1;
1080 bits<4> B2;
1081 bits<12> D2;
1082 bits<8> L2;
1084 let Inst{47-40} = op;
1085 let Inst{39-32} = L2;
1086 let Inst{31-28} = B1;
1087 let Inst{27-16} = D1;
1088 let Inst{15-12} = B2;
1089 let Inst{11-0} = D2;
1092 class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1094 field bits<48> Inst;
1095 field bits<48> SoftFail = 0;
1097 bits<4> B1;
1098 bits<12> D1;
1099 bits<4> B2;
1100 bits<12> D2;
1102 let Inst{47-32} = op;
1103 let Inst{31-28} = B1;
1104 let Inst{27-16} = D1;
1105 let Inst{15-12} = B2;
1106 let Inst{11-0} = D2;
1109 class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1111 field bits<48> Inst;
1112 field bits<48> SoftFail = 0;
1114 bits<4> B1;
1115 bits<12> D1;
1116 bits<4> B2;
1117 bits<12> D2;
1118 bits<4> R3;
1120 let Inst{47-40} = op{11-4};
1121 let Inst{39-36} = R3;
1122 let Inst{35-32} = op{3-0};
1123 let Inst{31-28} = B1;
1124 let Inst{27-16} = D1;
1125 let Inst{15-12} = B2;
1126 let Inst{11-0} = D2;
1129 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1131 field bits<32> Inst;
1132 field bits<32> SoftFail = 0;
1134 bits<4> B2;
1135 bits<12> D2;
1137 let Inst{31-16} = op;
1138 let Inst{15-12} = B2;
1139 let Inst{11-0} = D2;
1142 class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1144 field bits<48> Inst;
1145 field bits<48> SoftFail = 0;
1147 bits<5> V1;
1148 bits<16> I2;
1149 bits<4> M3;
1151 let Inst{47-40} = op{15-8};
1152 let Inst{39-36} = V1{3-0};
1153 let Inst{35-32} = 0;
1154 let Inst{31-16} = I2;
1155 let Inst{15-12} = M3;
1157 let Inst{10-8} = 0;
1158 let Inst{7-0} = op{7-0};
1161 class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1163 field bits<48> Inst;
1164 field bits<48> SoftFail = 0;
1166 bits<5> V1;
1167 bits<8> I2;
1168 bits<8> I3;
1169 bits<4> M4;
1171 let Inst{47-40} = op{15-8};
1172 let Inst{39-36} = V1{3-0};
1173 let Inst{35-32} = 0;
1174 let Inst{31-24} = I2;
1175 let Inst{23-16} = I3;
1176 let Inst{15-12} = M4;
1178 let Inst{10-8} = 0;
1179 let Inst{7-0} = op{7-0};
1182 class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1184 field bits<48> Inst;
1185 field bits<48> SoftFail = 0;
1187 bits<5> V1;
1188 bits<5> V3;
1189 bits<16> I2;
1190 bits<4> M4;
1192 let Inst{47-40} = op{15-8};
1193 let Inst{39-36} = V1{3-0};
1194 let Inst{35-32} = V3{3-0};
1195 let Inst{31-16} = I2;
1196 let Inst{15-12} = M4;
1199 let Inst{9-8} = 0;
1200 let Inst{7-0} = op{7-0};
1203 class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1205 field bits<48> Inst;
1206 field bits<48> SoftFail = 0;
1208 bits<5> V1;
1209 bits<5> V2;
1210 bits<5> V3;
1211 bits<8> I4;
1212 bits<4> M5;
1214 let Inst{47-40} = op{15-8};
1215 let Inst{39-36} = V1{3-0};
1216 let Inst{35-32} = V2{3-0};
1217 let Inst{31-28} = V3{3-0};
1218 let Inst{27-24} = 0;
1219 let Inst{23-16} = I4;
1220 let Inst{15-12} = M5;
1225 let Inst{7-0} = op{7-0};
1228 class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1230 field bits<48> Inst;
1231 field bits<48> SoftFail = 0;
1233 bits<5> V1;
1234 bits<5> V2;
1235 bits<12> I3;
1236 bits<4> M4;
1237 bits<4> M5;
1239 let Inst{47-40} = op{15-8};
1240 let Inst{39-36} = V1{3-0};
1241 let Inst{35-32} = V2{3-0};
1242 let Inst{31-20} = I3;
1243 let Inst{19-16} = M5;
1244 let Inst{15-12} = M4;
1247 let Inst{9-8} = 0;
1248 let Inst{7-0} = op{7-0};
1251 class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1253 field bits<48> Inst;
1254 field bits<48> SoftFail = 0;
1256 bits<5> V1;
1257 bits<5> V2;
1258 bits<5> V3;
1259 bits<8> I4;
1260 bits<4> M5;
1262 let Inst{47-40} = op{15-8};
1263 let Inst{39-36} = V1{3-0};
1264 let Inst{35-32} = V2{3-0};
1265 let Inst{31-28} = V3{3-0};
1266 let Inst{27-24} = 0;
1267 let Inst{23-20} = M5;
1268 let Inst{19-12} = I4;
1273 let Inst{7-0} = op{7-0};
1276 class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1278 field bits<48> Inst;
1279 field bits<48> SoftFail = 0;
1281 bits<5> V1;
1282 bits<5> V2;
1283 bits<8> I3;
1284 bits<8> I4;
1285 bits<4> M5;
1287 let Inst{47-40} = op{15-8};
1288 let Inst{39-36} = V1{3-0};
1289 let Inst{35-32} = V2{3-0};
1290 let Inst{31-24} = I4;
1291 let Inst{23-20} = M5;
1292 let Inst{19-12} = I3;
1295 let Inst{9-8} = 0;
1296 let Inst{7-0} = op{7-0};
1299 class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1301 field bits<48> Inst;
1302 field bits<48> SoftFail = 0;
1304 bits<5> V1;
1305 bits<16> I2;
1306 bits<4> I3;
1308 let Inst{47-40} = op{15-8};
1309 let Inst{39-36} = V1{3-0};
1310 let Inst{35-32} = 0;
1311 let Inst{31-16} = I2;
1312 let Inst{15-12} = I3;
1314 let Inst{10-8} = 0;
1315 let Inst{7-0} = op{7-0};
1318 class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1320 field bits<48> Inst;
1321 field bits<48> SoftFail = 0;
1323 bits<5> V1;
1324 bits<4> R2;
1325 bits<8> I3;
1326 bits<4> M4;
1328 let Inst{47-40} = op{15-8};
1329 let Inst{39-36} = V1{3-0};
1330 let Inst{35-32} = R2;
1331 let Inst{31-24} = 0;
1332 let Inst{23-20} = M4;
1333 let Inst{19-12} = I3;
1335 let Inst{10-8} = 0;
1336 let Inst{7-0} = op{7-0};
1339 // Depending on the instruction mnemonic, certain bits may be or-ed into
1341 class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1342 bits<4> m4or = 0>
1344 field bits<48> Inst;
1345 field bits<48> SoftFail = 0;
1347 bits<5> V1;
1348 bits<5> V2;
1349 bits<4> M3;
1350 bits<4> M4;
1351 bits<4> M5;
1353 let Inst{47-40} = op{15-8};
1354 let Inst{39-36} = V1{3-0};
1355 let Inst{35-32} = V2{3-0};
1356 let Inst{31-24} = 0;
1357 let Inst{23-20} = M5;
1361 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0});
1362 let Inst{15-12} = M3;
1365 let Inst{9-8} = 0;
1366 let Inst{7-0} = op{7-0};
1369 // Depending on the instruction mnemonic, certain bits may be or-ed into
1371 class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1372 bits<4> m5or = 0>
1374 field bits<48> Inst;
1375 field bits<48> SoftFail = 0;
1377 bits<5> V1;
1378 bits<5> V2;
1379 bits<5> V3;
1380 bits<4> M4;
1381 bits<4> M5;
1383 let Inst{47-40} = op{15-8};
1384 let Inst{39-36} = V1{3-0};
1385 let Inst{35-32} = V2{3-0};
1386 let Inst{31-28} = V3{3-0};
1387 let Inst{27-24} = 0;
1392 let Inst{19-16} = 0;
1393 let Inst{15-12} = M4;
1398 let Inst{7-0} = op{7-0};
1401 class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1403 field bits<48> Inst;
1404 field bits<48> SoftFail = 0;
1406 bits<5> V1;
1407 bits<5> V2;
1408 bits<5> V3;
1409 bits<4> M4;
1410 bits<4> M5;
1411 bits<4> M6;
1413 let Inst{47-40} = op{15-8};
1414 let Inst{39-36} = V1{3-0};
1415 let Inst{35-32} = V2{3-0};
1416 let Inst{31-28} = V3{3-0};
1417 let Inst{27-24} = 0;
1418 let Inst{23-20} = M6;
1419 let Inst{19-16} = M5;
1420 let Inst{15-12} = M4;
1425 let Inst{7-0} = op{7-0};
1428 // Depending on the instruction mnemonic, certain bits may be or-ed into
1430 class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1431 bits<4> m6or = 0>
1433 field bits<48> Inst;
1434 field bits<48> SoftFail = 0;
1436 bits<5> V1;
1437 bits<5> V2;
1438 bits<5> V3;
1439 bits<5> V4;
1440 bits<4> M5;
1441 bits<4> M6;
1443 let Inst{47-40} = op{15-8};
1444 let Inst{39-36} = V1{3-0};
1445 let Inst{35-32} = V2{3-0};
1446 let Inst{31-28} = V3{3-0};
1447 let Inst{27-24} = M5;
1452 let Inst{19-16} = 0;
1453 let Inst{15-12} = V4{3-0};
1458 let Inst{7-0} = op{7-0};
1461 class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1463 field bits<48> Inst;
1464 field bits<48> SoftFail = 0;
1466 bits<5> V1;
1467 bits<5> V2;
1468 bits<5> V3;
1469 bits<5> V4;
1470 bits<4> M5;
1471 bits<4> M6;
1473 let Inst{47-40} = op{15-8};
1474 let Inst{39-36} = V1{3-0};
1475 let Inst{35-32} = V2{3-0};
1476 let Inst{31-28} = V3{3-0};
1477 let Inst{27-24} = M6;
1478 let Inst{23-20} = 0;
1479 let Inst{19-16} = M5;
1480 let Inst{15-12} = V4{3-0};
1485 let Inst{7-0} = op{7-0};
1488 class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1490 field bits<48> Inst;
1491 field bits<48> SoftFail = 0;
1493 bits<5> V1;
1494 bits<4> R2;
1495 bits<4> R3;
1497 let Inst{47-40} = op{15-8};
1498 let Inst{39-36} = V1{3-0};
1499 let Inst{35-32} = R2;
1500 let Inst{31-28} = R3;
1501 let Inst{27-12} = 0;
1503 let Inst{10-8} = 0;
1504 let Inst{7-0} = op{7-0};
1507 class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1509 field bits<48> Inst;
1510 field bits<48> SoftFail = 0;
1512 bits<5> V1;
1514 let Inst{47-40} = op{15-8};
1515 let Inst{39-36} = 0;
1516 let Inst{35-32} = V1{3-0};
1517 let Inst{31-12} = 0;
1520 let Inst{9-8} = 0;
1521 let Inst{7-0} = op{7-0};
1524 class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1526 field bits<48> Inst;
1527 field bits<48> SoftFail = 0;
1529 bits<5> V1;
1530 bits<5> V2;
1531 bits<4> M3;
1533 let Inst{47-40} = op{15-8};
1534 let Inst{39-36} = 0;
1535 let Inst{35-32} = V1{3-0};
1536 let Inst{31-28} = V2{3-0};
1537 let Inst{27-24} = 0;
1538 let Inst{23-20} = M3;
1539 let Inst{19-12} = 0;
1544 let Inst{7-0} = op{7-0};
1547 class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1549 field bits<48> Inst;
1550 field bits<48> SoftFail = 0;
1552 bits<4> R1;
1553 bits<5> V2;
1554 bits<4> M3;
1555 bits<4> M4;
1557 let Inst{47-40} = op{15-8};
1558 let Inst{39-36} = R1;
1559 let Inst{35-32} = V2{3-0};
1560 let Inst{31-24} = 0;
1561 let Inst{23-20} = M3;
1562 let Inst{19-16} = M4;
1563 let Inst{15-12} = 0;
1566 let Inst{9-8} = 0;
1567 let Inst{7-0} = op{7-0};
1570 class InstVRRj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1572 field bits<48> Inst;
1573 field bits<48> SoftFail = 0;
1575 bits<5> V1;
1576 bits<5> V2;
1577 bits<5> V3;
1578 bits<4> M4;
1580 let Inst{47-40} = op{15-8};
1581 let Inst{39-36} = V1{3-0};
1582 let Inst{35-32} = V2{3-0};
1583 let Inst{31-28} = V3{3-0};
1584 let Inst{27-24} = 0;
1585 let Inst{23-20} = M4;
1586 let Inst{19-16} = 0;
1587 let Inst{15-12} = 0;
1592 let Inst{7-0} = op{7-0};
1595 class InstVRRk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1597 field bits<48> Inst;
1598 field bits<48> SoftFail = 0;
1600 bits<5> V1;
1601 bits<5> V2;
1602 bits<4> M3;
1604 let Inst{47-40} = op{15-8};
1605 let Inst{39-36} = V1{3-0};
1606 let Inst{35-32} = V2{3-0};
1607 let Inst{31-28} = 0;
1608 let Inst{27-24} = 0;
1609 let Inst{23-20} = M3;
1610 let Inst{19-16} = 0;
1611 let Inst{15-12} = 0;
1616 let Inst{7-0} = op{7-0};
1619 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1621 field bits<48> Inst;
1622 field bits<48> SoftFail = 0;
1624 bits<5> V1;
1625 bits<4> B2;
1626 bits<12> D2;
1627 bits<5> V3;
1628 bits<4> M4;
1630 let Inst{47-40} = op{15-8};
1631 let Inst{39-36} = V1{3-0};
1632 let Inst{35-32} = V3{3-0};
1633 let Inst{31-28} = B2;
1634 let Inst{27-16} = D2;
1635 let Inst{15-12} = M4;
1638 let Inst{9-8} = 0;
1639 let Inst{7-0} = op{7-0};
1642 class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1644 field bits<48> Inst;
1645 field bits<48> SoftFail = 0;
1647 bits<5> V1;
1648 bits<4> B2;
1649 bits<12> D2;
1650 bits<4> R3;
1651 bits<4> M4;
1653 let Inst{47-40} = op{15-8};
1654 let Inst{39-36} = V1{3-0};
1655 let Inst{35-32} = R3;
1656 let Inst{31-28} = B2;
1657 let Inst{27-16} = D2;
1658 let Inst{15-12} = M4;
1660 let Inst{10-8} = 0;
1661 let Inst{7-0} = op{7-0};
1664 class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1666 field bits<48> Inst;
1667 field bits<48> SoftFail = 0;
1669 bits<4> R1;
1670 bits<4> B2;
1671 bits<12> D2;
1672 bits<5> V3;
1673 bits<4> M4;
1675 let Inst{47-40} = op{15-8};
1676 let Inst{39-36} = R1;
1677 let Inst{35-32} = V3{3-0};
1678 let Inst{31-28} = B2;
1679 let Inst{27-16} = D2;
1680 let Inst{15-12} = M4;
1683 let Inst{9-8} = 0;
1684 let Inst{7-0} = op{7-0};
1687 class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1689 field bits<48> Inst;
1690 field bits<48> SoftFail = 0;
1692 bits<5> V1;
1693 bits<4> B2;
1694 bits<12> D2;
1695 bits<4> R3;
1697 let Inst{47-40} = op{15-8};
1698 let Inst{39-36} = 0;
1699 let Inst{35-32} = R3;
1700 let Inst{31-28} = B2;
1701 let Inst{27-16} = D2;
1702 let Inst{15-12} = V1{3-0};
1703 let Inst{11-9} = 0;
1705 let Inst{7-0} = op{7-0};
1708 class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1710 field bits<48> Inst;
1711 field bits<48> SoftFail = 0;
1713 bits<5> V1;
1714 bits<5> V2;
1715 bits<4> B2;
1716 bits<12> D2;
1717 bits<4> M3;
1719 let Inst{47-40} = op{15-8};
1720 let Inst{39-36} = V1{3-0};
1721 let Inst{35-32} = V2{3-0};
1722 let Inst{31-28} = B2;
1723 let Inst{27-16} = D2;
1724 let Inst{15-12} = M3;
1727 let Inst{9-8} = 0;
1728 let Inst{7-0} = op{7-0};
1731 class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1733 field bits<48> Inst;
1734 field bits<48> SoftFail = 0;
1736 bits<5> V1;
1737 bits<4> X2;
1738 bits<4> B2;
1739 bits<12> D2;
1740 bits<4> M3;
1742 let Inst{47-40} = op{15-8};
1743 let Inst{39-36} = V1{3-0};
1744 let Inst{35-32} = X2;
1745 let Inst{31-28} = B2;
1746 let Inst{27-16} = D2;
1747 let Inst{15-12} = M3;
1749 let Inst{10-8} = 0;
1750 let Inst{7-0} = op{7-0};
1753 class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1755 field bits<48> Inst;
1756 field bits<48> SoftFail = 0;
1758 bits<5> V1;
1759 bits<4> B2;
1760 bits<12> D2;
1761 bits<8> I3;
1763 let Inst{47-40} = op{15-8};
1764 let Inst{39-32} = I3;
1765 let Inst{31-28} = B2;
1766 let Inst{27-16} = D2;
1767 let Inst{15-12} = V1{3-0};
1768 let Inst{11-9} = 0;
1770 let Inst{7-0} = op{7-0};
1773 //===----------------------------------------------------------------------===//
1775 //===----------------------------------------------------------------------===//
1779 bits<16> enc;
1786 bits<32> enc;
1788 let Inst{31-24} = enc{31-24};
1789 let Inst{19-16} = enc{19-16};
1794 bits<48> enc;
1796 let Inst{47-40} = enc{47-40};
1797 let Inst{7-0} = enc{7-0};
1802 bits<48> enc;
1805 let Inst{47-40} = enc{47-40};
1806 let Inst{35-32} = enc{35-32};
1811 bits<48> enc;
1813 let Inst{47-40} = enc{47-40};
1814 let Inst{7-0} = enc{7-0};
1819 bits<16> enc;
1821 let Inst{15-8} = enc{15-8};
1826 bits<32> enc;
1828 let Inst{31-16} = enc{31-16};
1833 bits<32> enc;
1835 let Inst{31-16} = enc{31-16};
1840 bits<48> enc;
1842 let Inst{47-40} = enc{47-40};
1843 let Inst{7-0} = enc{7-0};
1848 bits<32> enc;
1850 let Inst{31-24} = enc{31-24};
1855 bits <48> enc;
1857 let Inst{47-40} = enc{47-40};
1858 let Inst{7-0} = enc{7-0};
1863 bits<32> enc;
1865 let Inst{31-24} = enc{31-24};
1870 bits<48> enc;
1872 let Inst{47-40} = enc{47-40};
1873 let Inst{7-0} = enc{7-0};
1878 bits<32> enc;
1880 let Inst{31-24} = enc{31-24};
1885 bits<48> enc;
1889 let Inst{47-40} = enc{47-40};
1890 let Inst{7-0} = enc{7-0};
1895 bits<48> enc;
1897 let Inst{47-40} = enc{47-40};
1898 let Inst{7-0} = enc{7-0};
1903 bits<48> enc;
1905 let Inst{47-40} = enc{47-40};
1906 let Inst{7-0} = enc{7-0};
1911 bits<32> enc;
1913 let Inst{31-16} = enc{31-16};
1918 bits<32> enc;
1920 let Inst{31-24} = enc{31-24};
1925 bits<48> enc;
1927 let Inst{47-40} = enc{47-40};
1928 let Inst{7-0} = enc{7-0};
1933 bits<48> enc;
1935 let Inst{47-32} = enc{47-32};
1940 bits<48> enc;
1942 let Inst{47-40} = enc{47-40};
1947 bits<48> enc;
1949 let Inst{47-32} = enc{47-32};
1954 bits<48> enc;
1956 let Inst{47-40} = enc{47-40};
1957 let Inst{35-32} = enc{35-32};
1962 bits<48> enc;
1964 let Inst{47-40} = enc{47-40};
1965 let Inst{7-0} = enc{7-0};
1970 bits<48> enc;
1972 let Inst{47-40} = enc{47-40};
1973 let Inst{7-0} = enc{7-0};
1978 bits<48> enc;
1980 let Inst{47-40} = enc{47-40};
1981 let Inst{7-0} = enc{7-0};
1986 bits<48> enc;
1988 let Inst{47-40} = enc{47-40};
1989 let Inst{7-0} = enc{7-0};
1994 bits<48> enc;
1996 let Inst{47-40} = enc{47-40};
1997 let Inst{7-0} = enc{7-0};
2002 bits<48> enc;
2004 let Inst{47-40} = enc{47-40};
2005 let Inst{7-0} = enc{7-0};
2009 //===----------------------------------------------------------------------===//
2011 //===----------------------------------------------------------------------===//
2014 // compare-and-branch instructions, or conditional move instructions),
2017 // - One used for code generation, which encodes the condition mask as an
2019 // - One pattern for the base form of the instruction with an explicit
2021 // - Specific patterns for each extended mnemonic, where the condition mask
2038 //===----------------------------------------------------------------------===//
2041 class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein,
2044 bits<4> ccmask = ccmaskin;
2062 // Condition masks for general instructions that can set all 4 bits.
2091 // Condition masks for integer instructions (e.g. compare-and-branch).
2125 //===----------------------------------------------------------------------===//
2127 //===----------------------------------------------------------------------===//
2132 // in which case the 4-bit condition-code mask is added as a final operand.
2242 // One 4-bit immediate operand and one address operand. The immediate
2246 // One 4-bit immediate operand and two address operands.
2256 //===----------------------------------------------------------------------===//
2258 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2266 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2270 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
2276 class StoreInherentS<string mnemonic, bits<16> opcode,
2277 SDPatternOperator operator, bits<5> bytes>
2284 class SideEffectInherentE<string mnemonic, bits<16>opcode>
2287 class SideEffectInherentS<string mnemonic, bits<16> opcode,
2294 class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
2301 class CallRI<string mnemonic, bits<12> opcode>
2306 class CallRIL<string mnemonic, bits<12> opcode>
2310 class CallRR<string mnemonic, bits<8> opcode>
2314 class CallRX<string mnemonic, bits<8> opcode>
2318 class CondBranchRI<string mnemonic, bits<12> opcode,
2326 class AsmCondBranchRI<string mnemonic, bits<12> opcode>
2330 class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
2339 class CondBranchRIL<string mnemonic, bits<12> opcode>
2345 class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
2349 class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
2357 class CondBranchRR<string mnemonic, bits<8> opcode>
2363 class AsmCondBranchRR<string mnemonic, bits<8> opcode>
2367 class NeverCondBranchRR<string mnemonic, bits<8> opcode>
2373 class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
2382 class CondBranchRX<string mnemonic, bits<8> opcode>
2389 class AsmCondBranchRX<string mnemonic, bits<8> opcode>
2394 class NeverCondBranchRX<string mnemonic, bits<8> opcode>
2401 class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
2409 class CondBranchRXY<string mnemonic, bits<16> opcode>
2417 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
2424 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
2435 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
2440 class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
2445 class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
2454 multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
2461 class CmpBranchRIEb<string mnemonic, bits<16> opcode,
2467 class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
2473 class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
2482 multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
2489 class CmpBranchRIEc<string mnemonic, bits<16> opcode,
2495 class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
2501 class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
2510 multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
2517 class CmpBranchRRFc<string mnemonic, bits<16> opcode,
2522 class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
2527 multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
2534 class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
2543 class CmpBranchRRS<string mnemonic, bits<16> opcode,
2549 class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
2555 class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
2565 multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
2572 class CmpBranchRIS<string mnemonic, bits<16> opcode,
2578 class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
2584 class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
2594 multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
2601 class CmpBranchRSYb<string mnemonic, bits<16> opcode,
2607 class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
2613 multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
2620 class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
2629 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2636 class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2643 class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2650 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2657 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2665 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2673 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2680 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2688 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2696 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2705 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2712 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2719 multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2720 bits<16> rsyOpcode, RegisterOperand cls> {
2729 class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2736 multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
2748 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2754 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2760 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2761 RegisterOperand cls, bits<5> bytes,
2772 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2773 RegisterOperand cls, bits<5> bytes,
2784 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2786 bits<5> bytes> {
2796 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2797 TypedReg tr, bits<5> bytes, bits<4> type = 0>
2807 class StoreVRXGeneric<string mnemonic, bits<16> opcode>
2814 multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> {
2815 let mayStore = 1, AccessBytes = 16 in {
2827 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2828 SDPatternOperator operator, bits<5> bytes>
2838 class StoreLengthVRSd<string mnemonic, bits<16> opcode,
2839 SDPatternOperator operator, bits<5> bytes>
2848 class StoreLengthVSI<string mnemonic, bits<16> opcode,
2849 SDPatternOperator operator, bits<5> bytes>
2858 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2865 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2872 multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2873 bits<16> rsyOpcode, RegisterOperand cls> {
2882 multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
2901 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2909 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2917 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2925 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2935 class StoreSSE<string mnemonic, bits<16> opcode>
2942 class CondStoreRSY<string mnemonic, bits<16> opcode,
2943 RegisterOperand cls, bits<5> bytes,
2953 // Like CondStoreRSY, but used for the raw assembly form. The condition-code
2955 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
2956 RegisterOperand cls, bits<5> bytes,
2965 class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
2966 RegisterOperand cls, bits<5> bytes,
2977 multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
2978 RegisterOperand cls, bits<5> bytes,
2985 class SideEffectUnaryI<string mnemonic, bits<8> opcode, ImmOpWithPattern imm>
2989 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2995 class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3002 class SideEffectUnaryS<string mnemonic, bits<16> opcode,
3003 SDPatternOperator operator, bits<5> bytes,
3011 class SideEffectUnarySIY<string mnemonic, bits<16> opcode,
3012 bits<5> bytes,
3021 class SideEffectAddressS<string mnemonic, bits<16> opcode,
3027 class LoadAddressRX<string mnemonic, bits<8> opcode,
3033 class LoadAddressRXY<string mnemonic, bits<16> opcode,
3039 multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
3040 bits<16> rxyOpcode, SDPatternOperator operator> {
3049 class LoadAddressRIL<string mnemonic, bits<12> opcode,
3055 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3064 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3073 class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
3081 class UnaryMemRRFc<string mnemonic, bits<16> opcode,
3090 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3096 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3102 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3108 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3114 class CondUnaryRSY<string mnemonic, bits<16> opcode,
3116 bits<5> bytes, AddressingMode mode = bdaddr20only>
3134 // Like CondUnaryRSY, but used for the raw assembly form. The condition-code
3136 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
3137 RegisterOperand cls, bits<5> bytes,
3149 class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
3150 RegisterOperand cls, bits<5> bytes,
3163 multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
3165 RegisterOperand cls, bits<5> bytes,
3172 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3173 RegisterOperand cls, bits<5> bytes,
3184 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3185 RegisterOperand cls, bits<5> bytes>
3196 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3197 RegisterOperand cls, bits<5> bytes,
3208 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3210 bits<5> bytes> {
3220 class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3221 TypedReg tr, ImmOpWithPattern imm, bits<4> type = 0>
3228 class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, ImmOpWithPattern imm>
3232 class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3233 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
3234 bits<4> m5 = 0, string fp_mnemonic = "">
3245 class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
3246 bits<4> m5 = 0>
3253 class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
3261 // The CC-setting form ends with "S" and sets the low bit of M5.
3264 multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
3267 TypedReg tr1, TypedReg tr2, bits<4> type> {
3281 multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
3291 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3292 TypedReg tr, bits<5> bytes, bits<4> type = 0>
3301 class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
3308 multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> {
3309 let mayLoad = 1, AccessBytes = 16 in {
3320 class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
3325 class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
3330 class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
3334 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3340 class SideEffectBinaryRRE<string mnemonic, bits<16> opcode,
3345 class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode,
3353 class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode,
3360 class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
3365 class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
3369 class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
3374 class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
3379 class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
3385 class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
3390 class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
3395 class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
3403 class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
3411 class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
3419 class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
3428 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3439 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3450 class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3459 class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3471 class UnaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3483 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3495 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
3507 class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3516 class BinaryRRFc<string mnemonic, bits<16> opcode,
3521 class BinaryMemRRFc<string mnemonic, bits<16> opcode,
3529 multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
3535 class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3540 class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3547 class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3563 // Like CondBinaryRRF, but used for the raw assembly form. The condition-code
3565 class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3575 class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
3586 multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
3593 class CondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3607 // Like CondBinaryRRFa, but used for the raw assembly form. The condition-code
3609 class AsmCondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3615 class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode,
3625 multiclass CondBinaryRRFaPair<string mnemonic, bits<16> opcode,
3633 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3642 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3648 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
3660 class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3672 // Like CondBinaryRIE, but used for the raw assembly form. The condition-code
3674 class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3684 class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
3695 multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
3702 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3711 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3722 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3728 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3739 class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3746 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3747 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3760 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3761 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3776 class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3778 SDPatternOperator load, bits<5> bytes>
3789 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3790 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3804 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3806 SDPatternOperator load, bits<5> bytes> {
3817 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3826 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3835 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
3836 bits<16> siyOpcode, SDPatternOperator operator,
3846 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3853 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3854 TypedReg tr, bits<4> type>
3861 class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
3866 class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3867 TypedReg tr1, TypedReg tr2, bits<4> type>
3875 class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
3880 class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3881 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
3890 class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
3895 class BinaryVRIh<string mnemonic, bits<16> opcode>
3900 class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3901 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
3910 class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3915 class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3916 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
3917 bits<4> modifier = 0>
3926 class BinaryExtraVRRb<string mnemonic, bits<16> opcode, bits<4> type = 0>
3932 class BinaryExtraVRRbGeneric<string mnemonic, bits<16> opcode>
3938 // The CC-setting form ends with "S" and sets the low bit of M5.
3939 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
3942 TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
3950 class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
3958 // The CC-setting form ends with "S" and sets the low bit of M5.
3961 multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
3964 TypedReg tr1, TypedReg tr2, bits<4> type> {
3978 multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3988 class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3989 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
3990 bits<4> m6 = 0, string fp_mnemonic = "">
4002 class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
4003 bits<4> m6 = 0>
4011 class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
4019 // The CC-setting form ends with "S" and sets the low bit of M5.
4020 multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
4023 TypedReg tr2, bits<4> type, bits<4> m5,
4024 bits<4> modifier = 0> {
4032 class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
4038 class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4044 class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4050 class BinaryVRRk<string mnemonic, bits<16> opcode>
4054 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4055 TypedReg tr1, TypedReg tr2, bits<4> type>
4064 class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
4069 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4070 bits<5> bytes>
4080 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4081 TypedReg tr, bits<4> type>
4089 class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
4094 class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4095 bits<5> bytes>
4104 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4105 TypedReg tr, bits<5> bytes>
4115 class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4116 bits<5> bytes, AddressingMode mode = bdaddr12only>
4123 class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4124 bits<5> bytes, AddressingMode mode = bdaddr20only>
4131 multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
4132 bits<16> rsyOpcode, RegisterOperand cls,
4133 bits<5> bytes> {
4143 class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
4151 class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4152 bits<5> bytes>
4161 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
4170 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
4171 SDPatternOperator operator, TypedReg tr, bits<5> bytes,
4181 class MemoryBinarySSd<string mnemonic, bits<8> opcode,
4188 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4198 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4208 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
4216 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
4224 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
4231 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
4237 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4238 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
4250 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4251 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
4263 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4264 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
4276 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
4278 SDPatternOperator load, bits<5> bytes> {
4289 class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4290 bits<5> bytes, AddressingMode mode = bdaddr12only>
4297 class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4298 bits<5> bytes, AddressingMode mode = bdaddr20only>
4305 multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4306 RegisterOperand cls, bits<5> bytes> {
4315 class CompareSSb<string mnemonic, bits<8> opcode>
4324 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4334 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4343 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4353 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
4365 class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4366 TypedReg tr, bits<4> type, string fp_mnemonic = "">
4378 class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
4386 class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4394 class CompareVRRh<string mnemonic, bits<16> opcode>
4400 class TestInherentS<string mnemonic, bits<16> opcode,
4407 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4415 class TestBinarySIL<string mnemonic, bits<16> opcode,
4421 class TestRSL<string mnemonic, bits<16> opcode>
4427 class TestVRRg<string mnemonic, bits<16> opcode>
4431 class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
4436 class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
4444 class SideEffectTernaryMemMemRRFa<string mnemonic, bits<16> opcode,
4455 class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode,
4463 class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
4475 class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
4481 multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode,
4488 class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
4498 multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
4505 class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
4512 class TernaryRRFa<string mnemonic, bits<16> opcode,
4518 class TernaryRRFb<string mnemonic, bits<16> opcode,
4528 class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4534 class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4545 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4546 bits<5> bytes, AddressingMode mode = bdaddr12only>
4557 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4558 bits<5> bytes, AddressingMode mode = bdaddr20only>
4569 multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4570 RegisterOperand cls, bits<5> bytes> {
4579 class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
4585 class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
4591 class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
4600 class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
4609 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4611 SDPatternOperator load, bits<5> bytes>
4625 class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4635 class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4636 TypedReg tr1, TypedReg tr2, bits<4> type>
4646 class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4651 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4652 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
4663 class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4668 class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4669 TypedReg tr1, TypedReg tr2, bits<4> type,
4670 SDPatternOperator m5mask, bits<4> m5or>
4682 // The CC-setting form ends with "S" and sets the low bit of M5.
4684 multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
4687 TypedReg tr1, TypedReg tr2, bits<4> type,
4688 bits<4> modifier = 0> {
4702 multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
4712 class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4724 class TernaryVRRcFloat<string mnemonic, bits<16> opcode,
4726 bits<4> type = 0, bits<4> m5 = 0>
4737 class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode>
4743 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4744 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m6 = 0>
4755 class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
4764 multiclass TernaryExtraVRRd<string mnemonic, bits<16> opcode,
4766 TypedReg tr1, TypedReg tr2, bits<4> type> {
4779 multiclass TernaryExtraVRRdGeneric<string mnemonic, bits<16> opcode> {
4790 class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4791 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0,
4805 class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
4810 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4811 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
4823 class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4828 class TernaryVRRj<string mnemonic, bits<16> opcode>
4833 class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
4842 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
4853 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4854 TypedReg tr1, TypedReg tr2, bits<5> bytes, ImmOpWithPattern index>
4867 class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4868 TypedReg tr1, TypedReg tr2, bits<4> type>
4881 class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
4890 class QuaternaryVRIf<string mnemonic, bits<16> opcode>
4896 class QuaternaryVRIg<string mnemonic, bits<16> opcode>
4902 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
4904 TypedReg tr3, TypedReg tr4, bits<4> type,
4905 SDPatternOperator m6mask = imm32zx4_timm, bits<4> m6or = 0>
4917 class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode>
4923 // The CC-setting form ends with "S" and sets the low bit of M6.
4925 multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
4928 TypedReg tr1, TypedReg tr2, bits<4> type,
4929 bits<4> modifier = 0> {
4945 multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
4953 class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode,
4959 multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode,
4968 class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode,
4974 multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
4982 class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
4989 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4998 class CmpSwapRRE<string mnemonic, bits<16> opcode,
5008 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
5020 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
5032 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
5042 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
5043 RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0>
5052 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
5058 class PrefetchRILPC<string mnemonic, bits<12> opcode,
5063 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
5069 class BranchPreloadSMI<string mnemonic, bits<8> opcode>
5075 class BranchPreloadMII<string mnemonic, bits<8> opcode>
5080 //===----------------------------------------------------------------------===//
5082 //===----------------------------------------------------------------------===//
5088 //===----------------------------------------------------------------------===//
5104 RegisterOperand cls, bits<5> bytes,
5153 // operand. The 3-address register instruction with a spilled source cannot
5154 // be converted directly to a target 2-address reg/mem instruction.
5155 // Mapping: <INSN>R -> MemFoldPseudo -> <INSN>
5156 class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes,
5172 class MemFoldPseudo_FP<string mnemonic, RegisterOperand cls, bits<5> bytes,
5178 class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes,
5193 class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes,
5216 SDPatternOperator load, bits<5> bytes,
5278 RegisterOperand cls, bits<5> bytes,
5298 class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
5309 bits<5> bytes, AddressingMode mode = bdxaddr20only>
5330 // the value of the PSW's 2-bit condition code field.
5360 // describe the second (non-memory) operand.
5458 //===----------------------------------------------------------------------===//
5460 //===----------------------------------------------------------------------===//
5462 multiclass BinaryRXYAndPseudo<string mnemonic, bits<16> opcode,
5464 SDPatternOperator load, bits<5> bytes,
5474 multiclass BinaryRXPairAndPseudo<string mnemonic, bits<8> rxOpcode,
5475 bits<16> rxyOpcode, SDPatternOperator operator,
5477 SDPatternOperator load, bits<5> bytes> {
5492 multiclass BinaryRXEAndPseudo<string mnemonic, bits<16> opcode,
5494 SDPatternOperator load, bits<5> bytes> {
5502 multiclass TernaryRXFAndPseudo<string mnemonic, bits<16> opcode,
5505 bits<5> bytes> {
5513 multiclass CondUnaryRSYPairAndMemFold<string mnemonic, bits<16> opcode,
5515 RegisterOperand cls, bits<5> bytes,
5523 RegisterOperand cls, bits<5> bytes,
5529 // Define an instruction that operates on two fixed-length blocks of memory,
5535 multiclass MemorySS<string mnemonic, bits<8> opcode, SDPatternOperator memop> {
5550 multiclass CompareMemorySS<string mnemonic, bits<8> opcode,
5566 // by the character in R0. The instruction processes a CPU-determinated
5570 multiclass StringRRE<string mnemonic, bits<16> opcode,