Lines Matching defs:BitShift

4559                                   SDValue &AlignedAddr, SDValue &BitShift,
4570   BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
4572   BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
4577                             DAG.getConstant(0, DL, WideVT), BitShift);
4608   SDValue AlignedAddr, BitShift, NegBitShift;
4609   getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift);
4626   SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
4633   SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
4704   SDValue AlignedAddr, BitShift, NegBitShift;
4705   getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift);
4709   SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
8565   Register BitShift = MI.getOperand(4).getReg();
8597   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
8608     .addReg(OldVal).addReg(BitShift).addImm(0);
8660   Register BitShift = MI.getOperand(4).getReg();
8695   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
8703     .addReg(OldVal).addReg(BitShift).addImm(0);
8762   Register BitShift = MI.getOperand(5).getReg();
8804   //   %OldValRot     = RLL %OldVal, BitSize(%BitShift)
8822     .addReg(OldVal).addReg(BitShift).addImm(BitSize);