Lines Matching +full:asi +full:- +full:format
1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "systemz-isel"
24 #define PASS_NAME "SystemZ DAG->DAG Pattern Instruction Selection"
47 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it.
79 Base.getNode()->dump(DAG);
86 Index.getNode()->dump(DAG);
103 return (uint64_t(1) << Count) - 1;
122 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
139 return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0));
147 return Subtarget->getInstrInfo();
182 // PC-relative address matching routines used by SystemZOperands.td.
263 // Try to match Addr as an address with a base, 12-bit displacement
325 // using block (SS-format) instructions.
329 // non-overlapping case. We also need to avoid full overlap (i.e. two
339 // if A[1 - I] == X and if N can use a block operation like NC from A[I]
344 // requirements for a PC-relative access.
366 if (F.getFnAttribute("fentry-call").getValueAsString() != "true") {
367 if (F.hasFnAttribute("mnop-mcount"))
368 report_fatal_error("mnop-mcount only supported with fentry-call");
369 if (F.hasFnAttribute("mrecord-mcount"))
370 report_fatal_error("mrecord-mcount only supported with fentry-call");
483 // Look through no-op truncations.
488 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
492 unsigned Op0Code = Op0->getOpcode();
493 unsigned Op1Code = Op1->getOpcode();
502 cast<ConstantSDNode>(Op0)->getSExtValue());
505 cast<ConstantSDNode>(Op1)->getSExtValue());
514 uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() -
515 cast<GlobalAddressSDNode>(Anchor)->getOffset());
551 if (Base->getOpcode() == ISD::FrameIndex)
574 // once. It should be a natural two-operand addition in that case.
575 if (Index->hasOneUse())
578 // Prefer addition if the second operation is sign-extended, in the
580 unsigned IndexOpcode = Index->getOpcode();
586 // Don't use LA for two-operand addition if either operand is only
588 if (Base->hasOneUse())
604 cast<ConstantSDNode>(Addr)->getSExtValue()))
639 if (N->getNodeId() == -1 ||
642 DAG->RepositionNode(Pos->getIterator(), N.getNode());
645 // Conservatively mark it with the same -abs(Id) to assure node id
647 N->setNodeId(Pos->getNodeId());
658 Base = CurDAG->getRegister(0, VT);
661 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
662 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
668 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base);
674 Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT);
686 Index = CurDAG->getRegister(0, VT);
732 Index = Regs[1 - I];
760 uint64_t AndMask = MaskNode->getZExtValue();
768 KnownBits Known = CurDAG->computeKnownBits(Op.getOperand(0));
781 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate));
783 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
794 Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)));
823 uint64_t Mask = MaskNode->getZExtValue();
828 KnownBits Known = CurDAG->computeKnownBits(Input);
846 uint64_t Mask = ~MaskNode->getZExtValue();
851 KnownBits Known = CurDAG->computeKnownBits(Input);
861 // Any 64-bit rotate left can be merged into the RxSBG.
868 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63;
874 // Bits above the extended operand are don't-care.
891 // Check that the extension bits are don't-care (i.e. are masked out
895 if (maskMatters(RxSBG, allOnes(BitSize) - allOnes(InnerBitSize))) {
899 RxSBG.Rotate += (BitSize - InnerBitSize);
913 uint64_t Count = CountNode->getZExtValue();
919 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom
925 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count))
940 uint64_t Count = CountNode->getZExtValue();
946 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
948 if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count)))
951 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
953 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count)))
957 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63;
967 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT);
974 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32,
977 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N);
984 EVT VT = N->getValueType(0);
1001 if (Count == 1 && N->getOpcode() != ISD::AND)
1006 // these ANDs into an RISBG later if a three-address instruction is useful.
1009 // Prefer AND for any 32-bit and-immediate operation.
1012 // As well as for any 64-bit operation that can be implemented via LLC(R),
1013 // LLH(R), LLGT(R), or one of the and-immediate instructions.
1023 if (Load->getMemoryVT() == MVT::i32 &&
1024 (Load->getExtensionType() == ISD::EXTLOAD ||
1025 Load->getExtensionType() == ISD::ZEXTLOAD) &&
1027 Subtarget->hasLoadAndZeroRightmostByte())
1035 SDValue Mask = CurDAG->getConstant(RISBG.Mask, DL, VT);
1036 SDValue New = CurDAG->getNode(ISD::AND, DL, VT, In, Mask);
1044 if (!N->isMachineOpcode())
1052 if (Subtarget->hasMiscellaneousExtensions())
1055 if (VT == MVT::i32 && Subtarget->hasHighWord() &&
1056 // We can only use the 32-bit instructions if all source bits are
1072 CurDAG->getTargetConstant(RISBG.Start, DL, MVT::i32),
1073 CurDAG->getTargetConstant(RISBG.End | 128, DL, MVT::i32),
1074 CurDAG->getTargetConstant(RISBG.Rotate, DL, MVT::i32)
1077 DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops), 0));
1084 EVT VT = N->getValueType(0);
1090 RxSBGOperands(Opcode, N->getOperand(0)),
1091 RxSBGOperands(Opcode, N->getOperand(1))
1095 while (RxSBG[I].Input->hasOneUse() && expandRxSBG(RxSBG[I]))
1112 SDValue Op0 = N->getOperand(I ^ 1);
1117 if (Load->getMemoryVT() == MVT::i8)
1125 if (Subtarget->hasMiscellaneousExtensions())
1132 CurDAG->getTargetConstant(RxSBG[I].Start, DL, MVT::i32),
1133 CurDAG->getTargetConstant(RxSBG[I].End, DL, MVT::i32),
1134 CurDAG->getTargetConstant(RxSBG[I].Rotate, DL, MVT::i32)
1137 DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, MVT::i64, Ops), 0));
1145 EVT VT = Node->getValueType(0);
1147 SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT);
1149 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
1169 SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT);
1170 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
1184 EVT VT = Node->getValueType(0);
1188 Ops.push_back(CurDAG->getTargetConstant(OpVal, DL, MVT::i32));
1189 SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops);
1194 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, DL, VT, Op);
1201 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode());
1210 SDValue CP = CurDAG->getTargetConstantPool(
1211 ConstantInt::get(Type::getInt128Ty(*CurDAG->getContext()), Val),
1212 TLI->getPointerTy(CurDAG->getDataLayout()));
1216 SDValue(CurDAG->getMachineNode(SystemZ::LARL, DL, PtrVT, CP), 0),
1217 CurDAG->getTargetConstant(0, DL, PtrVT),
1218 CurDAG->getRegister(0, PtrVT),
1219 CurDAG->getEntryNode()
1221 ResNode = CurDAG->getMachineNode(SystemZ::VL, DL, VT, MVT::Other, Ops);
1226 MachineFunction& MF = CurDAG->getMachineFunction();
1231 CurDAG->setNodeMemRefs(cast<MachineSDNode>(ResNode), {MemOp});
1236 SDValue ElemV = N->getOperand(2);
1241 unsigned Elem = ElemN->getZExtValue();
1242 EVT VT = N->getValueType(0);
1246 auto *Load = dyn_cast<LoadSDNode>(N->getOperand(1));
1247 if (!Load || !Load->hasNUsesOfValue(1, 0))
1249 if (Load->getMemoryVT().getSizeInBits() !=
1250 Load->getValueType(0).getSizeInBits())
1254 if (!selectBDVAddr12Only(Load->getBasePtr(), ElemV, Base, Disp, Index) ||
1260 N->getOperand(0), Base, Disp, Index,
1261 CurDAG->getTargetConstant(Elem, DL, MVT::i32), Load->getChain()
1263 SDNode *Res = CurDAG->getMachineNode(Opcode, DL, VT, MVT::Other, Ops);
1270 SDValue Value = Store->getValue();
1273 if (Store->getMemoryVT().getSizeInBits() != Value.getValueSizeInBits())
1283 unsigned Elem = ElemN->getZExtValue();
1288 if (!selectBDVAddr12Only(Store->getBasePtr(), ElemV, Base, Disp, Index) ||
1294 Vec, Base, Disp, Index, CurDAG->getTargetConstant(Elem, DL, MVT::i32),
1295 Store->getChain()
1297 ReplaceNode(Store, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
1312 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0))
1315 // Is the store non-extending and non-indexed?
1316 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1319 SDValue Load = StoredVal->getOperand(0);
1320 // Is the stored value a non-extending and non-indexed load?
1332 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1333 LoadNode->getOffset() != StoreNode->getOffset())
1338 SDValue Chain = StoreNode->getChain();
1343 InputChain = LoadNode->getChain();
1363 for (SDValue Op : StoredVal->ops())
1374 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
1394 SDValue StoredVal = StoreNode->getOperand(1);
1395 unsigned Opc = StoredVal->getOpcode();
1401 EVT MemVT = StoreNode->getMemoryVT();
1412 NewOpc = SystemZ::ASI;
1441 auto OperandV = OperandC->getAPIntValue();
1443 OperandV = -OperandV;
1446 Operand = CurDAG->getTargetConstant(OperandV, DL, MemVT);
1449 if (!selectBDAddr20Only(StoreNode->getBasePtr(), Base, Disp))
1454 CurDAG->getMachineNode(NewOpc, DL, MVT::i32, MVT::Other, Ops);
1455 CurDAG->setNodeMemRefs(
1456 Result, {StoreNode->getMemOperand(), LoadNode->getMemOperand()});
1460 CurDAG->RemoveDeadNode(Node);
1467 if (Load->getMemoryVT() != Store->getMemoryVT())
1471 if (Load->isVolatile() || Store->isVolatile())
1475 if (Load->isInvariant() && Load->isDereferenceable())
1479 const Value *V1 = Load->getMemOperand()->getValue();
1480 const Value *V2 = Store->getMemOperand()->getValue();
1485 uint64_t Size = Load->getMemoryVT().getStoreSize();
1486 int64_t End1 = Load->getSrcValueOffset() + Size;
1487 int64_t End2 = Store->getSrcValueOffset() + Size;
1491 return AA->isNoAlias(MemoryLocation(V1, End1, Load->getAAInfo()),
1492 MemoryLocation(V2, End2, Store->getAAInfo()));
1497 auto *Load = cast<LoadSDNode>(Store->getValue());
1501 uint64_t Size = Load->getMemoryVT().getStoreSize();
1504 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode()))
1507 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode()))
1517 auto *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I));
1518 auto *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I));
1519 return !LoadA->isVolatile() && LoadA->getMemoryVT() == LoadB->getMemoryVT() &&
1527 TypeSize StoreSize = MemAccess->getMemoryVT().getStoreSize();
1528 SDValue BasePtr = MemAccess->getBasePtr();
1529 MachineMemOperand *MMO = MemAccess->getMemOperand();
1534 if (MemAccess->getAlign().value() < StoreSize ||
1535 (LdSt && !LdSt->getOffset().isUndef()))
1539 if (MMO->getOffset() % StoreSize != 0)
1543 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1544 if ((PSV->isGOT() || PSV->isConstantPool()))
1552 if (GA->getOffset() % StoreSize != 0)
1556 const GlobalValue *GV = GA->getGlobal();
1557 const DataLayout &DL = GV->getDataLayout();
1558 if (GV->getPointerAlignment(DL).value() < StoreSize)
1568 ETy = L->getExtensionType();
1570 ETy = AL->getExtensionType();
1578 if (Node->isMachineOpcode()) {
1579 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
1580 Node->setNodeId(-1);
1584 unsigned Opcode = Node->getOpcode();
1587 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1593 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1598 // If this is a 64-bit operation in which both 32-bit halves are nonzero,
1601 if (Node->getValueType(0) == MVT::i64 &&
1602 Node->getOperand(0).getOpcode() != ISD::Constant)
1603 if (auto *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
1604 uint64_t Val = Op1->getZExtValue();
1606 // logical operations provided by miscellaneous-extensions-3.
1607 if (Subtarget->hasMiscellaneousExtensions3()) {
1608 unsigned ChildOpcode = Node->getOperand(0).getOpcode();
1610 if (Val == (uint64_t)-1 && Opcode == ISD::XOR)
1614 // Check whether this expression matches OR-with-complement
1617 auto Op0 = Node->getOperand(0);
1618 if (auto *Op0Op1 = dyn_cast<ConstantSDNode>(Op0->getOperand(1)))
1619 if (Op0Op1->getZExtValue() == (uint64_t)-1)
1623 // Don't split an XOR with -1 as LCGR/AGHI is more compact.
1624 if (Opcode == ISD::XOR && Op1->isAllOnes())
1627 splitLargeImmediate(Opcode, Node, Node->getOperand(0),
1628 Val - uint32_t(Val), uint32_t(Val));
1635 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1648 if (Node->getValueType(0) == MVT::i128) {
1650 SDValue Src = Node->getOperand(0);
1651 Src = CurDAG->getNode(ISD::BITCAST, DL, MVT::v16i8, Src);
1656 SDValue Res = SDValue(CurDAG->getMachineNode(SystemZ::VPERM, DL,
1659 Res = CurDAG->getNode(ISD::BITCAST, DL, MVT::i128, Res);
1669 // If this is a 64-bit constant that is out of the range of LLILF,
1670 // LLIHF and LGFI, split it into two 32-bit pieces.
1671 if (Node->getValueType(0) == MVT::i64) {
1672 uint64_t Val = Node->getAsZExtVal();
1674 splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val),
1679 if (Node->getValueType(0) == MVT::i128) {
1680 const APInt &Val = Node->getAsAPIntVal();
1694 SDValue Op0 = Node->getOperand(0);
1695 SDValue Op1 = Node->getOperand(1);
1699 (Subtarget->hasLoadStoreOnCond2() &&
1700 Node->getValueType(0).isInteger() &&
1701 Node->getValueType(0).getSizeInBits() <= 64 &&
1703 isInt<16>(cast<ConstantSDNode>(Op1)->getSExtValue()) &&
1705 isInt<16>(cast<ConstantSDNode>(Op0)->getSExtValue())))) {
1706 SDValue CCValid = Node->getOperand(2);
1707 SDValue CCMask = Node->getOperand(3);
1708 uint64_t ConstCCValid = CCValid.getNode()->getAsZExtVal();
1709 uint64_t ConstCCMask = CCMask.getNode()->getAsZExtVal();
1711 CCMask = CurDAG->getTargetConstant(ConstCCValid ^ ConstCCMask,
1713 SDValue Op4 = Node->getOperand(4);
1715 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
1726 EVT VT = Node->getValueType(0);
1749 APFloat Imm = cast<ConstantFPSDNode>(Node)->getValueAPF();
1763 unsigned ElemBitSize = Store->getValue().getValueSizeInBits();
1779 StoreSDNode *St = cast<StoreSDNode>(CurDAG->getTruncStore(
1780 AtomOp->getChain(), SDLoc(AtomOp), AtomOp->getVal(),
1781 AtomOp->getBasePtr(), AtomOp->getMemoryVT(), AtomOp->getMemOperand()));
1782 assert(St->getMemOperand()->isAtomic() && "Broken MMO.");
1786 if (AtomOp->getSuccessOrdering() == AtomicOrdering::SequentiallyConsistent)
1787 Chain = CurDAG->getMachineNode(SystemZ::Serialize, SDLoc(AtomOp),
1843 Subtarget->getRegisterInfo()->getPointerRegClass(*MF);
1845 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32);
1852 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1860 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1874 // IsProfitableToFold - Returns true if is profitable to fold the specific
1881 if (N.getOpcode() == ISD::LOAD && U->getOpcode() == SystemZISD::ICMP) {
1882 if (!N.hasOneUse() || !U->hasOneUse())
1889 SDNode *CCUser = *U->use_begin();
1891 if (CCUser->getOpcode() == ISD::CopyToReg ||
1892 cast<RegisterSDNode>(CCUser->getOperand(1))->getReg() == SystemZ::CC) {
1893 for (auto *U : CCUser->uses()) {
1905 if (CCRegUser->isMachineOpcode() &&
1906 CCRegUser->getMachineOpcode() == SystemZ::BRC)
1907 return !N->isPredecessorOf(CCUser->getOperand(0).getNode());
1947 // 0/-1 value, so it has priority over the other tests below.
1953 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1955 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1959 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1961 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1965 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1970 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1972 // Handle cases where adding a value forces a non-sign bit to contain
1977 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1981 // sign-based extractions above.
1983 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1986 TopBit - (3 << SystemZ::IPM_CC), 31);
1990 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1995 TopBit - (1 << SystemZ::IPM_CC), 31);
2001 auto *TrueOp = dyn_cast<ConstantSDNode>(Node->getOperand(0));
2002 auto *FalseOp = dyn_cast<ConstantSDNode>(Node->getOperand(1));
2005 if (FalseOp->getZExtValue() != 0)
2007 if (TrueOp->getSExtValue() != 1 && TrueOp->getSExtValue() != -1)
2010 auto *CCValidOp = dyn_cast<ConstantSDNode>(Node->getOperand(2));
2011 auto *CCMaskOp = dyn_cast<ConstantSDNode>(Node->getOperand(3));
2014 int CCValid = CCValidOp->getZExtValue();
2015 int CCMask = CCMaskOp->getZExtValue();
2018 SDValue CCReg = Node->getOperand(4);
2020 SDValue Result = CurDAG->getNode(SystemZISD::IPM, DL, MVT::i32, CCReg);
2023 Result = CurDAG->getNode(ISD::XOR, DL, MVT::i32, Result,
2024 CurDAG->getConstant(IPM.XORValue, DL, MVT::i32));
2027 Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result,
2028 CurDAG->getConstant(IPM.AddValue, DL, MVT::i32));
2030 EVT VT = Node->getValueType(0);
2032 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA;
2033 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result,
2034 CurDAG->getConstant(IPM.Bit, DL, MVT::i32));
2037 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result);
2039 if (TrueOp->getSExtValue() == 1) {
2041 Result = CurDAG->getNode(ISD::SRL, DL, VT, Result,
2042 CurDAG->getConstant(IPM.Bit, DL, MVT::i32));
2043 Result = CurDAG->getNode(ISD::AND, DL, VT, Result,
2044 CurDAG->getConstant(1, DL, VT));
2046 // Sign-extend from IPM.Bit using a pair of shifts.
2047 int ShlAmt = VT.getSizeInBits() - 1 - IPM.Bit;
2048 int SraAmt = VT.getSizeInBits() - 1;
2049 Result = CurDAG->getNode(ISD::SHL, DL, VT, Result,
2050 CurDAG->getConstant(ShlAmt, DL, MVT::i32));
2051 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result,
2052 CurDAG->getConstant(SraAmt, DL, MVT::i32));
2060 EVT VT = N->getValueType(0);
2062 return N->getFlags().hasAllowReassociation() &&
2063 N->getFlags().hasNoSignedZeros() && Subtarget->hasVector() &&
2064 (VT != MVT::f32 || Subtarget->hasVectorEnhancements1()) &&
2065 !N->isStrictFPOpcode();
2071 if (Subtarget->hasLoadStoreOnCond2())
2076 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
2077 E = CurDAG->allnodes_end();
2080 if (N->use_empty())
2084 switch (N->getOpcode()) {
2093 LLVM_DEBUG(N->dump(CurDAG));
2095 LLVM_DEBUG(Res.getNode()->dump(CurDAG));
2098 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
2104 CurDAG->RemoveDeadNodes();