Lines Matching defs:Disp
115 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
124 const MCExpr *Disp;
190 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
197 Op->Mem.Disp = Disp;
272 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true);
275 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true);
312 addExpr(Inst, Mem.Disp);
318 addExpr(Inst, Mem.Disp);
325 addExpr(Inst, Mem.Disp);
332 addExpr(Inst, Mem.Disp);
339 addExpr(Inst, Mem.Disp);
428 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
739 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
988 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
991 const MCExpr *&Disp, const MCExpr *&Length,
994 if (getParser().parseExpression(Disp))
1104 const MCExpr *Disp;
1109 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1193 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,