Lines Matching defs:Cond

193                             SmallVectorImpl<MachineOperand> &Cond) {
197   // Push the branch opcode into Cond too so later in insertBranch
199   Cond.push_back(MachineOperand::CreateImm(Opc));
200   Cond.push_back(MachineOperand::CreateImm(CC));
206       Cond.push_back(MachineOperand::CreateReg(Reg, false));
247                                    SmallVectorImpl<MachineOperand> &Cond,
268       parseCondBranch(LastInst, TBB, Cond);
302     parseCondBranch(SecondLastInst, TBB, Cond);
330                                       ArrayRef<MachineOperand> Cond,
334   assert((Cond.size() <= 3) &&
337   if (Cond.empty()) {
346   unsigned Opc = Cond[0].getImm();
347   unsigned CC = Cond[1].getImm();
349     Register Reg = Cond[2].getReg();
394     SmallVectorImpl<MachineOperand> &Cond) const {
395   assert(Cond.size() <= 3);
396   SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm());
397   Cond[1].setImm(GetOppositeBranchCondition(CC));